MT40A256M16GE-062E Datasheet, PDF (151/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
SELF REFRESH Operation
Figure 87: Self Refresh Entry/Exit Timing with CAL Mode
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Notes:
1. ^tCAL = 3nCK, ^tCPDED = 4nCK, ^tCKSRE/^tCKSRE_PAR = 8nCK, ^tCKSRX = 8nCK, ^tXS_FAST =
t_{REFC4 (MIN) + 10ns.}
2. CS_n = HIGH, ACT_n = "Don't Care," RAS_n/A16 = "Don't Care," CAS_n/A15 = "Don't
Care," WE_n/A14 = "Don't Care."
3. Only MRS (limited to those described in the SELF REFRESH Operations section), ZQCS, or
ZQCL commands are allowed.
Self Refresh Abort
The exit timing from self refresh exit to the first valid command not requiring a locked
DLL is ^tXS. The value of ^tXS is (^tRFC + 10ns). This delay allows any refreshes started by
the device time to complete. ^tRFC continues to grow with higher density devices, so ^tXS
will grow as well. An MRS bit enables the self refresh abort mode. If the bit is disabled,
the controller uses ^tXS timings (location MR4, bit 9). If the bit is enabled, the device
aborts any ongoing refresh and does not increment the refresh counter. The controller
can issue a valid command not requiring a locked DLL after a delay of ^tXS_ABORT.
Upon exit from self refresh, the device requires a minimum of one extra REFRESH com-
mand before it is put back into self refresh mode. This requirement remains the same
irrespective of the setting of the MRS bit for self refresh abort.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
151
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