MT40A256M16GE-062E Datasheet, PDF (176/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
Data Bus Inversion
Table 62: DBI Write, DQ Frame Format (x16) (Continued)
Function
UDM_n or
UDBI_n
0
UDM0 or
UDBI0
1
UDM1 or
UDBI1
Transfer, Lower (L) and Upper(U)
2
3
4
5
UDM2 or
UDBI2
UDM3 or
UDBI3
UDM4 or
UDBI4
UDM5 or
UDBI5
6
UDM6 or
UDBI6
7
UDM7 or
UDBI7
DBI During a READ Operation
If the number of 0 data bits within a given byte lane is greater than four during a READ
operation, the DRAM inverts read data on its DQ outputs and drives the DBI_n pin
LOW; otherwise, the DRAM does not invert the read data and drives the DBI_n pin
HIGH. The read DQ frame format is shown below for x8 and x16 configurations (the x4
configuration does not support the DBI function).
Table 63: DBI Read, DQ Frame Format (x8)
Function
DQ[7:0]
DBI_n
0
Byte 0
DBI0
1
Byte 1
DBI1
2
Byte 2
DBI2
Transfer Byte
3
4
Byte 3
Byte 4
DBI3
DBI4
5
Byte 5
DBI5
6
Byte 6
DBI6
7
Byte 7
DBI7
Table 64: DBI Read, DQ Frame Format (x16)
Function
DQ[7:0]
LDBI_n
DQ[15:8]
UDBI_n
0
LByte 0
LDBI0
UByte 0
UDBI0
1
LByte 1
LDBI1
UByte 1
UDBI1
Transfer Byte, Lower (L) and Upper(U)
2
3
4
5
LByte 2
LByte 3
LByte 4
LByte 5
LDBI2
LDBI3
LDBI4
LDBI5
UByte 2
UByte 3
UByte 4
UByte 5
UDBI2
UDBI3
UDBI4
UDBI5
6
LByte 6
LDBI6
UByte 6
UDBI6
7
LByte 7
LDBI7
UByte 7
UDBI7
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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