MT40A256M16GE-062E Datasheet, PDF (185/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
Bank Access Operation
Bank Access Operation
DDR4 supports bank grouping: x4/x8 DRAMs have four bank groups (BG[1:0]), and
each bank group is comprised of four subbanks (BA[1:0]); x16 DRAMs have two bank
groups (BG[0]), and each bank group is comprised of four subbanks. Bank accesses to
different banks' groups require less time delay between accesses than bank accesses to
within the same bank's group. Bank accesses to different bank groups require ^tCCD_S
(or short) delay between commands while bank accesses within the same bank group
require ^tCCD_L (or long) delay between commands.
Figure 115: Bank Group x4/x8 Block Diagram
Bank 3
Bank 2
Bank 1
Bank 0
Memory Array
Bank 3
Bank 2
Bank 1
Bank 0
Memory Array
CMD/ADDR
CMD/ADDR
register
Bank Group 0
Sense amplifiers
Bank Group 1
Sense amplifiers
Bank 3
Bank 2
Bank 1
Bank 0
Memory Array
Bank Group 2
Sense amplifiers
Bank 3
Bank 2
Bank 1
Bank 0
Memory Array
Bank Group 3
Sense amplifiers
Local I/O gating
Local I/O gating
Local I/O gating
Local I/O gating
Global I/O gating
Data I/O
Notes: 1. Bank accesses to different bank groups require ^tCCD_S.
2. Bank accesses within the same bank group require ^tCCD_L.
Table 69: DDR4 Bank Group Timing Examples
Parameter
t_{CCD_S}
t_{CCD_L}
DDR4-1600
4nCK
4nCK or 6.25ns
DDR4-2133
4nCK
4nCK or 5.355ns
t_{RRD_S (½K)}
t_{RRD_L (½K)}
4nCK or 5ns
4nCK or 6ns
4nCK or 3.7ns
4nCK or 5.3ns
t_{RRD_S (1K)}
t_{RRD_L (1K)}
4nCK or 5ns
4nCK or 6ns
4nCK or 3.7ns
4nCK or 5.3ns
t_{RRD_S (2K)}
t_{RRD_L (2K)}
4nCK or 6ns
4nCK or 7.5ns
4nCK or 5.3ns
4nCK or 6.4ns
DDR4-2400
4nCK
4nCK or 5ns
4nCK or 3.3ns
4nCK or 4.9ns
4nCK or 3.3ns
4nCK or 4.9ns
4nCK or 5.3ns
4nCK or 6.4ns
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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