MT40A256M16GE-062E Datasheet, PDF (133/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
Post Package Repair
Figure 74: hPPR WR – Entry
7
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Figure 75: hPPR WR – Repair and Exit
CK_c
CK_t
CMD
Te0
Tf0
ACT
WR
Tg0
Tg1
Th0
Th1
DES
DES
DES
DES
Tj0
Tj1
Tj2
Tk0
Tk1
Tm0
Tm1
Tn0
DES
DES
DES
PRE
DES
MRSx
DES
Valid
BG
BGf
BGf
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Valid
N/A
Valid
N/A
Valid
BA
BAf
BAf
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Valid
N/A
Valid
N/A
Valid
ADDR
Valid
Valid
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Valid
N/A
Valid
(A13 = 0)
N/A
Valid
CKE
DQS_t
DQS_c
DQs1
All Banks
Precharged
and idle state
WL = CWL + AL + PL
4nCK
tRCD
hPPR Repair
bit 0 bit 1
bit 6 bit 7
tPGM
hPPR Repair
hPPR Repair
tPGM_Exit
hPPR Recognition
tPGMPST
hPPR Exit
Normal
mode
Don’t Care
Table 41: DDR4 hPPR Timing Parameters DDR4-1600 through DDR4-3200
Parameter
hPPR programming time
hPPR precharge exit time
hPPR exit time
Symbol
t_PGM
x4, x8
x16
t_{PGM_Exit}
t_PGMPST
Min
1000
2000
15
50
Max
–
–
–
–
Unit
ms
ms
ns
μs
sPPR Row Repair
Soft post package repair (sPPR) is a way to quickly, but temporarily, repair a row ele-
ment in a bank on a DRAM device, where hPPR takes longer but permanently repairs a
row element. sPPR mode is entered in a similar fashion as hPPR, sPPR uses MR4[5]
while hPPR uses MR4[13]. sPPR is disabled with MR4[5] = 0, which is the normal state,
and sPPR is enabled with MR4[5] = 1, which is the sPPR enabled state.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
133
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