PIC16LC63A-04 Datasheet, PDF(94/184 Page) Microchip Technology – 8-Bit CMOS Microcontrollers with A/D Converter

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PIC16LC63A-04 Datasheet, PDF (94/184 Pages) Microchip Technology – 8-Bit CMOS Microcontrollers with A/D Converter

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PIC16C63A/65B/73B/74B

FIGURE 13-5:

INTERRUPT LOGIC

PSPIF

PSPIE

ADIF

ADIE

RCIF

RCIE

CCP2IF

CCP2IE

TXIF

TXIE

SSPIF

SSPIE

CCP1IF

CCP1IE

TMR2IF

TMR2IE

TMR1IF

TMR1IE

T0IF

T0IE

INTF

INTE

RBIF

RBIE

PEIE

GIE

Wake-up (If in SLEEP mode)

Interrupt to CPU

The following table shows which devices have which interrupts.

Device T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF CCP2IF

PIC16C63A Yes Yes Yes

â Yes Yes Yes

Yes

PIC16C65B Yes Yes Yes Yes

â Yes Yes Yes

Yes

PIC16C73B Yes Yes Yes

Yes Yes Yes Yes

Yes

PIC16C74B Yes Yes Yes Yes Yes Yes Yes Yes

Yes

13.5.1 INT INTERRUPT

The external interrupt on RB0/INT pin is edge trig-

gered: either rising if bit INTEDG (OPTION_REG<6>)

is set, or falling if the INTEDG bit is clear. When a valid

edge appears on the RB0/INT pin, flag bit INTF

(INTCON<1>) is set. This interrupt can be disabled by

clearing enable bit INTE (INTCON<4>). Flag bit INTF

must be cleared in software in the Interrupt Service

Routine before re-enabling this interrupt. The INT inter-

rupt can wake-up the processor from SLEEP, if bit INTE

was set prior to going into SLEEP. The status of global

interrupt enable bit GIE decides whether or not the pro-

cessor branches to the interrupt vector following wake-

up. See Section 13.8 for details on SLEEP mode.

13.5.2 TMR0 INTERRUPT

An overflow (FFh â 00h) in the TMR0 register will set

flag bit T0IF (INTCON<2>). The interrupt can be

enabled/disabled by setting/clearing enable bit T0IE

(INTCON<5>) (see Section 6.0).

13.5.3 PORTB INTERRUPT-ON-CHANGE

An input change on PORTB<7:4> sets flag bit RBIF

(INTCON<0>). The interrupt can be enabled/disabled

by setting/clearing enable bit RBIE (INTCON<4>).

(Section 5.2)

Note:

If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the RBIF inter-

rupt flag may not get set.

DS30605C-page 94

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