PIC16LC63A-04 Datasheet, PDF (29/184 Pages) Microchip Technology – 8-Bit CMOS Microcontrollers with A/D Converter

PIC16C63A/65B/73B/74B
5.0 I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
5.1 PORTA and TRISA Registers
PORTA is a 6-bit latch.
The RA4/T0CKI pin is a Schmitt Trigger input and an
open drain output. All other RA port pins have TTL
input levels and full CMOS output drivers. All pins have
data direction bits (TRIS registers), which can config-
ure these pins as output or input.
Setting a TRISA register bit puts the corresponding out-
put driver in a hi-impedance mode. Clearing a bit in the
TRISA register puts the contents of the output latch on
the selected pin(s).
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified and then written to the port
data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin.
On the PIC16C73B/74B, PORTA pins are multiplexed
with analog inputs and analog VREF input. The opera-
tion of each pin is selected by clearing/setting the con-
trol bits in the ADCON1 register (A/D Control
Register1).
Note: On all RESETS, pins with analog functions
are configured as analog and digital inputs.
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 5-1:
INITIALIZING PORTA
(PIC16C73B/74B)
BCF
CLRF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
STATUS, RP0
PORTA
STATUS, RP0
0x06
ADCON1
0xCF
TRISA
;
; Initialize PORTA by
; clearing output
; data latches
; Select Bank 1
; Configure all pins
; as digital inputs
; Value used to
; initialize data
; direction
; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6> are always
; read as ’0’.
FIGURE 5-1:
BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
Data
Bus
WR
Port
D
Q
CK Q
Data Latch
D
Q
VDD
P
N
I/O pin⁽¹⁾
WR
TRIS
CK Q
TRIS Latch
VSS
Analog
Input
mode
RD TRIS
Q
D
TTL
Input
Buffer
EN
RD Port
To A/D Converter
Note 1: I/O pins have protection diodes to VDD and VSS.
FIGURE 5-2:
BLOCK DIAGRAM OF
RA4/T0CKI PIN
Data
Bus
WR
Port
DQ
CK Q
Data Latch
N
I/O pin⁽¹⁾
WR
TRIS
DQ
CK Q
TRIS Latch
VSS
Schmitt
Trigger
Input
Buffer
RD Port
RD TRIS
Q
D
ENEN
TMR0 Clock Input
Note 1: I/O pins have protection diodes to VDD and VSS.
 2000 Microchip Technology Inc.
DS30605C-page 29