PIC16LC63A-04 Datasheet, PDF (132/184 Pages) Microchip Technology – 8-Bit CMOS Microcontrollers with A/D Converter

PIC16C63A/65B/73B/74B
FIGURE 16-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
70
71
72
83
78
79
80
79
78
SDO
MSb
BIT6 - - - - - -1
LSb
SDI
Note:
75, 76
MSb IN
74
73
BIT6 - - - -1
Refer to Figure 16-4 for load conditions.
77
LSb IN
TABLE 16-10: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)
Param
No.
Symbol
Characteristic
Min
Typ† Max Units Conditions
70 TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TCY
— — ns
71 TscH
71A
SCK input high time
(Slave mode)
Continuous
Single Byte
1.25TCY + 30 — — ns
40
— — ns (Note 1)
72 TscL
72A
SCK input low time
(Slave mode)
Continuous
Single Byte
1.25TCY + 30 — — ns
40
— — ns (Note 1)
73 TdiV2scH, Setup time of SDI data input to SCK edge
100
TdiV2scL
— — ns
73A TB2B
Last clock edge of Byte1 to the 1st clock
edge of Byte2
1.5TCY + 40 — —
ns (Note 1)
74 TscH2diL, Hold time of SDI data input to SCK edge
100
— — ns
TscL2diL
75 TdoR
SDO data output rise time PIC16CXX
—
10 25 ns
PIC16LCXX
20 45 ns
76 TdoF
SDO data output fall time
—
10 25 ns
77 TssH2doZ _{SS↑ to SDO output hi-impedance}
78 TscR
SCK output rise time
PIC16CXX
(Master mode)
PIC16LCXX
10
— 50 ns
—
10 25 ns
20 45 ns
79 TscF
SCK output fall time (Master mode)
—
10 25 ns
80 TscH2doV, SDO data output valid
TscL2doV after SCK edge
PIC16CXX
PIC16LCXX
—
— 50 ns
— 100 ns
83 TscH2ssH, _{SS ↑ after SCK edge}
TscL2ssH
1.5TCY + 40 — — ns
† Data in “Typ” column is at 5 V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
DS30605C-page 132
 2000 Microchip Technology Inc.