PIC16LC63A-04 Datasheet, PDF(71/184 Page) Microchip Technology – 8-Bit CMOS Microcontrollers with A/D Converter

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

PIC16LC63A-04 Datasheet, PDF (71/184 Pages) Microchip Technology – 8-Bit CMOS Microcontrollers with A/D Converter

◁

PIC16C63A/65B/73B/74B

Steps to follow when setting up an Asynchronous

Reception:

1. Initialize the SPBRG register for the appropriate

baud rate. If a high speed baud rate is desired,

set bit BRGH. (Section 11.1).

2. Enable the asynchronous serial port by clearing

bit SYNC, and setting bit SPEN.

3. If interrupts are desired, set interrupt enable bits

RCIE (PIE1<5>), PEIE (INTCON<6>), and GIE

(INTCON<7>), as required.

4. If 9-bit reception is desired, then set bit RX9.

5. Enable the reception by setting bit CREN.

6. Flag bit RCIF will be set when reception is com-

plete and an interrupt will be generated if enable

bit RCIE was set.

7. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

8. Read the 8-bit received data by reading the

RCREG register.

9. If any error occurred, clear the error by clearing

enable bit CREN.

FIGURE 11-5:

RX (pin)

Rcv shift

reg

Rcv buffer reg

Read Rcv

buffer reg

RCREG

RCIF

(interrupt flag)

OERR bit

CREN

ASYNCHRONOUS RECEPTION

START

bit bit0 bit1

START

bit7/8 STOP bit bit0

bit

Word 1

RCREG

START

bit7/8 STOP bit

bit

Word 2

RCREG

bit7/8 STOP

bit

Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the

third word, causing the OERR (overrun) bit to be set. An overrun error indicates an error in userâs firmware.

TABLE 11-4: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2

Bit 1

Bit 0

Value on:

POR,

BOR

Value on

all other

RESETS

0Bh,8Bh

0Ch

INTCON GIE PEIE T0IE

PIR1

PSPIF(1) ADIF(2) RCIF

INTE RBIE T0IF INTF RBIF 0000 000x

TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000

18h

RCSTA SPEN RX9 SREN CREN â FERR OERR RX9D 0000 -00x

1Ah

RCREG USART Receive register

0000 0000

8Ch

PIE1

PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000

98h

TXSTA CSRC TX9 TXEN SYNC â BRGH TRMT TX9D 0000 -010

99h

SPBRG Baud Rate Generator register

0000 0000

Legend: u = unchanged, x = unknown, - = unimplemented locations read as '0'.

Shaded cells are not used for asynchronous reception.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76; always maintain these bits clear.

2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.

0000 000u

0000 0000

0000 -00x

0000 0000

0000 -010

0000 0000

DS30605C-page 71

▷