PIC16LC63A-04 Datasheet, PDF(63/184 Page) Microchip Technology – 8-Bit CMOS Microcontrollers with A/D Converter

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PIC16LC63A-04 Datasheet, PDF (63/184 Pages) Microchip Technology – 8-Bit CMOS Microcontrollers with A/D Converter

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PIC16C63A/65B/73B/74B

10.3.1.3 Transmission

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

be sent on the ninth bit and pin RC3/SCK/SCL is held

low. The transmit data must be loaded into the

SSPBUF register, which also loads the SSPSR regis-

ter. Then pin RC3/SCK/SCL should be enabled by set-

ting bit CKP (SSPCON<4>). The master must monitor

the SCL pin prior to asserting another clock pulse. The

slave devices may be holding off the master by stretch-

ing the clock. The eight data bits are shifted out on the

falling edge of the SCL input. This ensures that the

SDA signal is valid during the SCL high time

(Figure 10-7).

An SSP interrupt is generated for each data transfer

byte. Flag bit SSPIF must be cleared in software, and

the SSPSTAT register is used to determine the status

of the byte. Flag bit SSPIF is set on the falling edge of

the ninth clock pulse.

As a slave-transmitter, the ACK pulse from the

master-receiver is latched on the rising edge of the

ninth SCL input pulse. If the SDA line was high (not

ACK), then the data transfer is complete. When the

ACK is latched by the slave, the slave logic is reset

(resets SSPSTAT register) and the slave then monitors

for another occurrence of the START bit. If the SDA line

was low (ACK), the transmit data must be loaded into

the SSPBUF register, which also loads the SSPSR reg-

ister. Then pin RC3/SCK/SCL should be enabled by

setting bit CKP.

FIGURE 10-7:

I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

SDA

Receiving Address

R/W = 1

A7 A6 A5 A4 A3 A2 A1

ACK

Transmitting Data ACK

D7 D6 D5 D4 D3 D2 D1 D0

SCL

1 23456789

1234 56789

Data in

SCL held low

sampled

while CPU

responds to SSPIF

SSPIF (PIR1<3>)

Cleared in software

BF (SSPSTAT<0>)

From SSP Interrupt

SSPBUF is written in software Service Routine

CKP (SSPCON<4>)

Set bit after writing to SSPBUF

(the SSPBUF must be written to

before the CKP bit can be set)

DS30605C-page 63

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