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PIC16LC63A-04 Datasheet, PDF (133/184 Pages) Microchip Technology – 8-Bit CMOS Microcontrollers with A/D Converter | |||
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PIC16C63A/65B/73B/74B
FIGURE 16-15:
SS
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
70
SCK
(CKP = 0)
83
71
72
SCK
(CKP = 1)
80
SDO
MSb
BIT6 - - - - - -1
LSb
75, 76
77
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
Note: Refer to Figure 16-4 for load conditions.
TABLE 16-11: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Typâ Max Units
Conditions
70 TssL2scH, SSâ to SCKâ or SCKâ input
TssL2scL
71 TscH
71A
SCK input high time
(Slave mode)
Continuous
Single Byte
72 TscL
72A
SCK input low time
(Slave mode)
Continuous
Single Byte
TCY
â â ns
1.25TCY + 30 â â ns
40
â â ns (Note 1)
1.25TCY + 30 â â ns
40
â â ns (Note 1)
73A TB2B
Last clock edge of Byte1 to the 1st clock 1.5TCY + 40
edge of Byte2
74
TscH2diL,
TscL2diL Hold time of SDI data input to SCK edge
100
75 TdoR
SDO data output rise
time
PIC16CXX
PIC16LCXX
â
76 TdoF
SDO data output fall time
â
77 TssH2doZ SSâ to SDO output hi-impedance
10
78 TscR
SCK output rise time PIC16CXX
â
(Master mode)
PIC16LCXX
â
79 TscF
SCK output fall time (Master mode)
â
80
TscH2doV, SDO data output valid PIC16CXX
TscL2doV after SCK edge
PIC16LCXX
â
â
82 TssL2doV SDO data output valid PIC16CXX
â
after SSâ edge
PIC16LCXX
â
83
TscH2ssH,
TscL2ssH SS â after SCK edge
1.5TCY + 40
â â ns (Note 1)
â â ns
10 25 ns
20 45 ns
10 25 ns
â 50 ns
10 25 ns
20 45 ns
10 25 ns
â 50 ns
â 100 ns
â 50 ns
â 100 ns
â â ns
â Data in âTypâ column is at 5 V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
 2000 Microchip Technology Inc.
DS30605C-page 133
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