PIC32MX795F512L-80IPT Datasheet, PDF (9/68 Pages) Microchip Technology – PIC32 Flash Programming Specification

PIC32
5.1 Programming Interface
Figure 5-2 shows the basic programming interface in
PIC32 devices. Descriptions of each interface block are
provided in subsequent sections.
FIGURE 5-2:
BASIC PIC32 PROGRAMMING INTERFACE BLOCK DIAGRAM
TMS
TCK
TDI
TDO
or
PGECx
PGEDx
ETAP
MTAP
2-wire
to
4-wire
CPU
Flash
Controller
Flash
Memory
Common
VDD
VSS
MCLR
5.1.1 ETAP
This block serially feeds instructions and data into the
CPU.
5.1.2 MTAP
In addition to the EJTAG TAP (ETAP) controller, the
PIC32 device uses a second proprietary TAP controller
for additional operations. The Microchip TAP (MTAP)
controller supports two instructions relevant to
programming: MTAP_COMMAND and TAP switch
Instructions. See Table 19-1 for a complete list of
Instructions. The MTAP_COMMAND instruction provides
a mechanism for a JTAG probe to send commands to
the device through its Data register.
The programmer sends commands by shifting in the
MTAP_COMMAND instruction through the SendCommand
pseudo operation, and then sending MTAP_COMMAND
DR commands through XferData pseudo operation
(see Table 19-2 for specific commands).
The probe does not need to issue a MTAP_COMMAND
instruction for every command shifted into the Data
register.
5.1.3 2-WIRE TO 4-WIRE
This block converts the 2-wire ICSP interface to the
4-wire JTAG interface.
5.1.4 CPU
The CPU executes instructions at 8 MHz through the
internal oscillator.
5.1.5 FLASH CONTROLLER
The Flash controller controls erasing and programming
of the Flash memory on the device.
5.1.6 FLASH MEMORY
The PIC32 device Flash memory is divided into two
logical Flash partitions consisting of the Boot Flash
Memory (BFM) and Program Flash Memory (PFM).
The BFM begins at address 0x1FC00000, and the PFM
begins at address 0x1D000000. Each Flash partition is
divided into pages, which represent the smallest block
of memory that can be erased. Depending on the
device, page sizes are 256 words (1024 bytes), 1024
words (4096 bytes), or 4096 words (16,384 bytes).
Row size indicates the number of words that are pro-
grammed with the row program command. There are
always 8 rows within a page; therefore, devices with
256, 1024, and 4096 word page sizes have 32, 128,
and 512 word row sizes, respectively. Table 5-1 shows
the PFM, BFM, Row, and Page size of each device
family.
The highest memory locations of the BFM are reserved
for the device Configuration registers (see
Section 18.0 “Configuration Memory and Device
ID” for details).
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DS61145L-page 9