PIC32MX795F512L-80IPT Datasheet, PDF (5/68 Pages) Microchip Technology – PIC32 Flash Programming Specification

PIC32
4.0 CONNECTING TO THE DEVICE
The PIC32 family provides two possible physical
interfaces for connecting to and programming the
memory contents (Figure 4-1). For all programming
interfaces, the target device must be properly powered
and all required signals must be connected. In addition,
the interface must be enabled, either through its
Configuration bit, as in the case of the JTAG 4-wire
interface, or though a special initialization sequence, as
is the case for the 2-wire ICSP interface.
The JTAG interface is enabled by default in blank
devices shipped from the factory.
Enabling ICSP is described in Section 7.0 “Entering
2-Wire Enhanced ICSP Mode”.
FIGURE 4-1:
PROGRAMMING
INTERFACES
Programmer
2-wire
ICSP™
OR
4-wire
JTAG
+ MCLR, VDD, VSS
PIC32
4.1 4-wire Interface
One possible interface is the 4-wire JTAG (IEEE
1149.1) port. Table 4-1 lists the required pin
connections. This interface uses the following four
communication lines to transfer data to and from the
PIC32 device being programmed:
• TCK – Test Clock Input
• TMS – Test Mode Select Input
• TDI – Test Data Input
• TDO – Test Data Output
These signals are described in the following four
sections. Refer to the specific device data sheet for the
connection of the signals to the device pins.
4.1.1 TEST CLOCK INPUT (TCK)
TCK is the clock that controls the updating of the TAP
controller and the shifting of data through the Instruc-
tion or selected Data register(s). TCK is independent of
the processor clock with respect to both frequency and
phase.
4.1.2 TEST MODE SELECT INPUT (TMS)
TMS is the control signal for the TAP controller. This
signal is sampled on the rising edge of TCK.
4.1.3 TEST DATA INPUT (TDI)
TDI is the test data input to the Instruction or selected
Data register(s). This signal is sampled on the rising
edge of TCK for some TAP controller states.
4.1.4 TEST DATA OUTPUT (TDO)
TDO is the test data output from the Instruction or Data
register(s). This signal changes on the falling edge of
TCK. TDO is only driven when data is shifted out,
otherwise the TDO is tri-stated.
TABLE 4-1: 4-WIRE INTERFACE PINS
Device Pin Name
Pin Type
Pin Description
MCLR
ENVREG⁽²⁾
VDD and AVDD⁽¹⁾
VSS and AVSS⁽¹⁾
I
Programming Enable
I
Enable for On-Chip Voltage Regulator
P
Power Supply
P
Ground
VCAP
P
CPU logic filter capacitor connection
TDI
I
Test Data In
TDO
O
Test Data Out
TCK
I
Test Clock
TMS
I
Test Mode State
Legend: I = Input
O = Output
P = Power
Note 1: All power supply and ground pins must be connected, including analog supplies (AVDD) and ground
(AVSS).
2: The ENVREG pin is not available on all devices. Please refer to the “Pin Diagrams” section in the
specific device data sheet to determine availability.
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DS61145L-page 5