PIC32MX795F512L-80IPT Datasheet, PDF (57/68 Pages) Microchip Technology – PIC32 Flash Programming Specification

19.2 EJTAG TAP Controller
19.2.1 ETAP_ADDRESS COMMAND
ETAP_ADDRESS selects the Address register. The
read-only Address register provides the address for a
processor access. The value read in the register is
valid if a processor access is pending, otherwise the
value is undefined.
The two or three Least Significant Bytes (LSBs) of the
register are used with the Psz field from the EJTAG
Control register to indicate the size and data position of
the pending processor access transfer. These bits are
not taken directly from the address referenced by the
load/store.
19.2.2 ETAP_DATA COMMAND
ETAP_DATA selects the Data register. The read/write
Data register is used for op code and data transfers
during processor accesses. The value read in the Data
register is valid only if a processor access for a write is
pending, in which case the Data register holds the store
value. The value written to the Data register is only
used if a processor access for a pending read is
finished afterwards; in which case, the data value
written is the value for the fetch or load. This behavior
implies that the Data register is not a memory location
where a previously written value can be read
afterwards.
PIC32
19.2.3 ETAP_CONTROL COMMAND
ETAP_CONTROL selects the Control register. The
EJTAG Control register (ECR) handles processor Reset
and soft Reset indication, Debug mode indication,
access start, finish and size, and read/write indication.
The ECR also provides the following features:
• Controls debug vector location and indication of
serviced processor accesses
• Allows a debug interrupt request
• Indicates a processor low-power mode
• Allows implementation-dependent processor and
peripheral Resets
19.2.3.1 EJTAG Control Register (ECR)
The EJTAG Control register (see Register 19-1) is not
updated/written in the Update-DR state unless the
Reset occurred; that is ROCC (bit 31) is either already
‘0’ or is written to ‘0’ at the same time. This condition
ensures proper handling of processor accesses after a
Reset.
Reset of the processor can be indicated through the
ROCC bit in the TCK domain a number of TCK cycles
after it is removed in the processor clock domain in
order to allow for proper synchronization between the
two clock domains.
Bits that are Read/Write (R/W) in the register return
their written value on a subsequent read, unless other
behavior is defined.
Internal synchronization ensures that a written value is
updated for reading immediately afterwards, even
when the TAP controller takes the shortest path from
the Update-DR to Capture-DR state.
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DS61145L-page 57