PIC32MX795F512L-80IPT Datasheet, PDF (62/68 Pages) Microchip Technology – PIC32 Flash Programming Specification

PIC32
APPENDIX C: REVISION HISTORY
Revision A (August 2007)
This is the initial released version of the document.
Revision B (February 2008)
Update records for this revision are not available.
Revision C (April 2008)
Update records for this revision are not available.
Revision D (May 2008)
Update records for this revision are not available.
Revision E (July 2009)
This version of the document includes the following
additions and updates:
• Minor changes to style and formatting have been
incorporated throughout the document
• Added the following devices:
- PIC32MX565F256H
- PIC32MX575F512H
- PIC32MX675F512H
- PIC32MX795F512H
- PIC32MX575F512L
- PIC32MX675F512L
- PIC32MX795F512L
• Updated MCLR pulse line to show active-high
(P20) in Figure 7-1
• Updated Step 7 of Table 11-1 to clarify repeat of
the last instruction in the step
• The following instructions in Table 13-1 were
updated:
- Seventh, ninth and eleventh instructions in
Step 1
- All instructions in Step 2
- First instruction in Step 3
- Third instruction in Step 4
• Added the following devices to Table 17-1:
- PIC32MX565F256H
- PIC32MX575F512H
- PIC32MX575F512L
- PIC32MX675F512H
- PIC32MX675F512L
- PIC32MX795F512H
- PIC32MX795F512L
• Updated address values in Table 17-2
Revision E (July 2009) (Continued)
• Added the following devices to Table 17-5:
- PIC32MX565F256H
- PIC32MX575F512H
- PIC32MX675F512H
- PIC32MX795F512H
- PIC32MX575F512L
- PIC32MX675F512L
- PIC32MX795F512L
• Added Notes 1-3 and the following bits to the
DEVCFG - Device Configuration Word Summary
and the DEVCFG3: Device Configuration Word 3
(see Table 18-1 and Register ):
- FVBUSIO
- FUSBIDIO
- FCANIO
- FETHIO
- FMIIEN
- FPBDIV<1:0>
- FJTAGEN
• Updated the DEVID Summary (see Table 18-1)
• Updated ICESEL bit description and added the
FJTAGEN bit in DEVCFG0: Device Configuration
Word 0 (see Register 16-1)
• Updated DEVID: Device and Revision ID register
• Added Device IDs and Revision table (Table 18-4)
• Added MCLR High Time (parameter P20) to
Table 20-1
• Added Appendix B: “Hex File Format” and
Appendix D: “Revision History”
Revision F (April 2010)
This version of the document includes the following
additions and updates:
• The following global bit name changes were
made:
- NVMWR renamed as WR
- NVMWREN renamed as WREN
- NVMERR renamed as WRERR
- FVBUSIO renamed as FVBUSONIO
- FUPLLEN renamed as UPLLEN
- FUPLLIDIV renamed as UPLLIDIV
- POSCMD renamed as POSCMOD
• Updated the PIC32MX family data sheet
references in the fourth paragraph of Section 2.0
“Programming Overview”
• Updated the note in Section 5.2.2 “2-Phase
ICSP”
• Updated the Initiate Flash Row Write Op Codes and
instructions (see steps 4, 5 and 6 in Table 13-1)
DS61145L-page 62
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