PIC32MX795F512L-80IPT Datasheet, PDF(56/68 Page) Microchip Technology

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PIC32MX795F512L-80IPT Datasheet, PDF (56/68 Pages) Microchip Technology – PIC32 Flash Programming Specification

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PIC32

TABLE 19-2: MTAP_COMMAND DR COMMANDS

Command

Value

Description

MCHP_STATUS

MCHP_ASSERT_RST

MCHP_DE_ASSERT_RST

MCHP_ERASE

MCHP_FLASH_ENABLE(1)

MCHP_FLASH_DISABLE(1)

8âh0x00

8âh0xD1

8âh0xD0

8âh0xFC

8âh0xFE

8âh0xFD

NOP and return Status.

Requests the reset controller to assert device Reset.

Removes the request for device Reset, which causes the reset

controller to de-assert device Reset if there is no other source

requesting Reset (i.e., MCLR).

Cause the Flash controller to perform a Chip Erase.

Enables fetches and loads to the Flash (from the processor).

Disables fetches and loads to the Flash (from the processor).

Note 1: This command is not required for PIC32MZ EC family devices.

TABLE 19-3: MCHP STATUS VALUE

Bit

Range

Bit 7

Bit 6

Bit 5

7:0

CPS

NVMERR(1)

Bit 4

Bit 3

Bit 2

CFGRDY FCBUSY

bit 7 CPS: Code-Protect State bit

1 = Device is not code-protected

0 = Device is code-protected

bit 6 Unimplemented: Read as â0â

bit 5

NVMERR: NVMCON Status bit(1)

1 = An Error occurred during NVM operation

0 = An Error did not occur during NVM operation

bit 4 Unimplemented: Read as â0â

bit 3 CFGRDY: Code-Protect State bit

1 = Configuration has been read and CP is valid

0 = Configuration has not been read

bit 2 FCBUSY: Flash Controller Busy bit

1 = Flash controller is busy (Erase is in progress)

0 = Flash controller is not busy (either erase has not started or it has finished)

bit 1

FAEN: Flash Access Enable bit(2)

This bit reflects the state of CFGCON.FAEN.

1 = Flash access is enabled

0 = Flash access is disabled (i.e., processor accesses are blocked)

bit 0 DEVRST: Device Reset State bit

1 = Device Reset is active

0 = Device Reset is not active

Note 1: This bit is not implemented in PIC32MX320/340/360/420/440/460 devices.

2: This bit is not implemented in PIC32MZ EC family devices.

Bit 1

FAEN(2)

Bit 0

DEVRST

TABLE 19-4: EJTAG TAP INSTRUCTIONS

Command

Value

Description

ETAP_ADDRESS

ETAP_DATA

ETAP_CONTROL

ETAP_EJTAGBOOT

ETAP_FASTDATA

5âh0x08

5âh0x09

5âh0x0A

5âh0x0C

5âh0x0E

Select Address register.

Select Data register.

Select EJTAG Control register.

Set EjtagBrk, ProbEn and ProbTrap to â1â as the reset value.

Selects the Data and Fastdata registers.

DS61145L-page 56

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