PIC32MX795F512L-80IPT Datasheet, PDF (29/68 Pages) Microchip Technology – PIC32 Flash Programming Specification

The following steps are required to initiate a Flash
write:
1. XferInstruction (op code).
2. Repeat Step 1 until the last instruction is
transferred to the CPU.
TABLE 13-1: INITIATE FLASH ROW WRITE
OP CODES FOR PIC32
DEVICES
Op Code Instruction
Step 1:
All PIC32 devices: Initialize constants. Registers
a1, a2, and a3 are set for WREN = 1 or
NVMOP<3:0> = 0011, WR = 1 and WREN = 1,
respectively. Registers s1 and s2 are set for the
unlock data values and S0 is initialized to ‘0’.
34054003
34068000
34074000
3c11aa99
36316655
3c125566
365299aa
3c100000
ori a1,$0,0x4003
ori a2,$0,0x8000
ori a3,$0,0x4000
lui s1,0xaa99
ori s1,s1,0x6655
lui s2,0x5566
ori s2,s2,0x99aa
lui s0,0x0000
Step 2: PIC32MX devices only: Set register a0 to the
base address of the NVM register (0xBF80_F400).
3c04bf80
3484f400
lui a0,0xbf80
ori a0,a0,0xf400
Step 2:
PIC32MZ EC devices only: Set register a0 to the
base address of the NVM register (0xBF80_0600).
Register s3 is set for the value used to disable
write protection in NVMBPB.
3c04bf80
34840600
34158080
lui a0,0xbf80
ori a0,a0,0x0600
ori s3,$0,0x8080
Step 3: PIC32MZ EC devices only: Unlock and disable
Boot Flash write protection.
AC910010
AC920010
AC950090
00000000
sw s1,16(a0)
sw s2,16(a0)
sw s3,144(a0)
nop
Step 4: All PIC32 devices: Set the NVMADDR register
with the address of the Flash row to be
programmed.
3c08<ADDR>
3508<ADDR>
ac880020
lui t0,<FLASH_ROW_ADDR(31:16)>
ori t0,t0,<FLASH_ROW_ADDR(15:0)>
sw t0,32(a0)
Step 5: PIC32MX devices only: Set the NVMSRCADDR
register with the physical source SRAM address
(offset is 64).
3610<ADDR>
ac900040
ori s0,s0,<RAM_ADDR(15:0)>
sw s0,64(a0)
PIC32
TABLE 13-1: INITIATE FLASH ROW WRITE
OP CODES FOR PIC32
DEVICES (CONTINUED)
Op Code Instruction
Step 5: PIC32MZ EC devices only: Set the
NVMSRCADDR register with the physical source
SRAM address (offset is 112).
3610<ADDR>
ac900040
ori s0,s0,<RAM_ADDR(15:0)>
sw s0,112(a0)
Step 6: All PIC32 devices: Set up the NVMCON register
for write operation.
ac850000
sw a1,0(a0)
delay (6 μs)
Step 7: PIC32MX devices only: Poll the LVDSTAT
register.
8C880000
31080800
1500fffd
00000000
here1:
lw t0,0(a0)
andi t0,t0,0x0800
bne t0,$0,here1
nop
Step 8: All PIC32 devices: Unlock the NVMCON register
and start the write operation.
ac910010
ac920010
ac860008
sw s1,16(a0)
sw s2,16(a0)
sw a2,8(a0)
Step 9: All PIC32 devices: Loop until the WR bit
(NVMCON<15>) is clear.
8c880000
01064024
1500fffd
00000000
here2:
lw t0,0(a0)
and t0,t0,a2
bne t0,$0,here2
nop
Step 10: All PIC32 devices: Wait at least 500 ns after
seeing a ‘0’ in the WR bit (NVMCON<15>) before
writing to any of the NVM registers. This requires
inserting a NOP in the execution. The following
example assumes that the core is executing at
8 MHz; therefore, four NOP instructions equate to
500 ns.
00000000
nop
00000000
nop
00000000
nop
00000000
nop
Step 11: All PIC32 devices: Clear the WREN bit
(NVMCONM<14>).
ac870004
sw a3,4(a0)
Step 12: All PIC32 devices: Check the WRERR bit
(NVMCON<13>) to ensure that the program
sequence has completed successfully. If an error
occurs, jump to the error processing routine.
8c880000
lw t0,0(a0)
30082000
andi t0,zero,0x2000
1500<ERR_PROC> bne t0, $0, <err_proc_offset>
00000000
nop
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DS61145L-page 29