PIC32MX795F512L-80IPT Datasheet, PDF (59/68 Pages) Microchip Technology – PIC32 Flash Programming Specification

19.2.4 ETAP_EJTAGBOOT COMMAND
The ETAP_EJTAGBOOT command causes the
processor to fetch code from the debug exception
vector after a reset. This allows the programmer to
send instructions to the processor to execute, instead
of the processor fetching them from the normal reset
vector. The Reset value of the EjtagBrk, ProbTrap, and
ProbE bits follows the setting of the internal
EJTAGBOOT indication.
If the EJTAGBOOT instruction has been given, and the
internal EJTAGBOOT indication is active, then the
Reset value of the three bits is set (‘1’), otherwise the
Reset value is clear (‘0’).
The results of setting these bits are:
• Setting the EjtagBrk causes a Debug interrupt
exception to be requested right after the
processor Reset from the EJTAGBOOT instruction
• The debug handler is executed from the EJTAG
memory because ProbTrap is set to indicate
debug vector in EJTAG memory at 0xFF200200
• Service of the processor access is indicated
because ProbEn is set
With this configuration in place, an interrupt exception
will occur and the processor will fetch the handler from
the DMSEG at 0xFF200200. Since ProbEn is set, the
processor will wait for the instruction to be provided by
the probe.
PIC32
19.2.5 ETAP_FASTDATA COMMAND
The ETAP_FASTDATA command provides a
mechanism for quickly transferring data between the
processor and the probe. The width of the Fastdata
register is one bit. During a fast data access, the
Fastdata register is written and read (i.e., a bit is shifted
in and a bit is shifted out). During a fast data access,
the Fastdata register value shifted in specifies whether
the fast data access should be completed or not. The
value shifted out is a flag that indicates whether the fast
data access was successful or not (if completion was
requested). The FASTDATA access is used for efficient
block transfers between the DMSEG segment (on the
probe) and target memory (on the processor). An
“upload” is defined as a sequence that the processor
loads from target memory and stores to the DMSEG
segment. A “download” is a sequence of processor
loads from the DMSEG segment and stores to target
memory. The “Fastdata area” specifies the legal range
of DMSEG segment addresses (0xFF200000 to
0xFF20000F) that can be used for uploads and
downloads. The Data and Fastdata registers (selected
with the FASTDATA instruction) allow efficient
completion of pending Fastdata area accesses.
During Fastdata uploads and downloads, the
processor will stall on accesses to the Fastdata area.
The PrAcc (processor access pending bit) will be ‘1’
indicating the probe is required to complete the access.
Both upload and download accesses are attempted by
shifting in a zero SPrAcc value (to request access
completion) and shifting out SPrAcc to see if the
attempt will be successful (i.e., there was an access
pending and a legal Fastdata area address was used).
Downloads will also shift in the data to be used to
satisfy the load from the DMSEG segment Fastdata
area, while uploads will shift out the data being stored
to the DMSEG segment Fastdata area.
As noted above, two conditions must be true for the
Fastdata access to succeed. These are:
• PrAcc must be ‘1’ (i.e., there must be a pending
processor access)
• The Fastdata operation must use a valid Fastdata
area address in the DMSEG segment
(0xFF200000 to 0xFF20000F)
 2007-2013 Microchip Technology Inc.
DS61145L-page 59