PIC32MX795F512L-80IPT Datasheet, PDF (14/68 Pages) Microchip Technology – PIC32 Flash Programming Specification

PIC32
5.3 2-wire ICSP Details
In ICSP mode, the 2-wire ICSP signals are time
multiplexed into the 2-wire to 4-wire block. The 2-wire
to 4-wire block then converts the signals to look like a
4-wire JTAG port to the TAP controller.
There are two possible modes of operation:
• 4-phase ICSP
• 2-phase ICSP
5.3.1 4-PHASE ICSP
In 4-phase ICSP mode, the TDI, TDO and TMS device
pins are multiplexed onto PGEDx in four clocks (see
Figure 5-4). The Least Significant bit (LSb) is shifted
first; and TDI and TMS are sampled on the falling edge
FIGURE 5-4:
2-WIRE, 4-PHASE
of PGECx, while TDO is driven on the falling edge of
PGECx. The 4-phase ICSP mode is used for both read
and write data transfers.
5.3.2 2-PHASE ICSP
In 2-phase ICSP mode, the TMS and TDI device pins
are multiplexed into PGEDx in two clocks (see
Figure 5-5). The LSb is shifted first; and TDI and TMS
are sampled on the falling edge of PGECx. There is no
TDO output provided in this mode. The 2-phase ICSP
mode was designed to accelerate 2-wire, write-only
transactions.
Note:
The packet is not actually executed until the
first clock of the next packet. To enter 2-wire,
2-phase ICSP mode, the TDOEN bit
(DDPCON<0>) must be set to ‘0’.
TCK
TMS
‘1’
TDI
TDO
‘1’
‘0’
‘0’
IR0
1
‘1’
IR4
X
‘1’
‘0’
PGECx
PGEDx
pTDO = 1
TDI = IR0 TMS = 0
FIGURE 5-5:
2-WIRE, 2-PHASE
TCK
TMS
‘1’
‘1’
‘0’
‘0’
TDI
IR0
TDO
1
nTDO = 0
‘1’
IR4
X
‘1’
‘0’
PGECx
PGEDx
TDI = IR0 TMS = 0
DS61145L-page 14
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