PIC18F2221_1 Datasheet, PDF (87/402 Pages) Microchip Technology – Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2221/2321/4221/4321 FAMILY
EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
PROGRAM_MEMORY
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
BSF
DECFSZ
GOTO
BCF
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
COUNTER_HI
PROGRAM_LOOP
EECON1, WREN
; disable interrupts
; required sequence
; write 55h
; write AAh
; start program (CPU stall)
; re-enable interrupts
; loop until done
; disable write to memory
7.5.2 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
7.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT Time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
7.5.4
PROTECTION AGAINST
SPURIOUS WRITES
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 24.0 “Special Features of the
CPU” for more detail.
7.6 Flash Program Operation During
Code Protection
See Section 24.5 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TABLE 7-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values on
page
TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 55
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
55
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
55
TABLAT Program Memory Table Latch
55
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE TMR0IF INT0IF
RBIF
55
EECON2 EEPROM Control Register 2 (not a physical register)
57
EECON1 EEPGD CFGS
—
FREE WRERR WREN
WR
RD
57
IPR2
OSCFIP CMIP
—
EEIP
BCLIP HLVDIP TMR3IP CCP2IP
58
PIR2
OSCFIF CMIF
—
EEIF
BCLIF HLVDIF TMR3IF CCP2IF
58
PIE2
OSCFIE CMIE
—
EEIE
BCLIE HLVDIE TMR3IE CCP2IE
58
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
© 2009 Microchip Technology Inc.
DS39689F-page 87