PIC18F2221_1 Datasheet, PDF (264/402 Pages) Microchip Technology – Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2221/2321/4221/4321 FAMILY
REGISTER 24-5:
CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
R/P-1
R/P-0
U-0
U-0
r-0
R/P-1
U-0
R/P-1
DEBUG XINST BBSIZ1 BBSIZ0
—
LVP
—
STVREN
bit 7
bit 0
bit 7
bit 6
bit 5-4
DEBUG: Background Debugger Enable bit
1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0 = Background debugger enabled, RB6 and RB7 are dedicated to in-circuit debug
XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
BBSIZ<1:0>: Boot Block Size Select bits
PIC18F4221/4321 Devices:
1x = 1024 Words
01 = 512 Words
00 = 256 Words
PIC18F2221/2321 Devices:
1x = 512 Words
x1 = 512 Words
00 = 256 Words
bit 3 Reserved: Maintain as ‘0’
bit 2 LVP: Single-Supply ICSP™ Enable bit
1 = Single-Supply ICSP enabled
0 = Single-Supply ICSP disabled
bit 1 Unimplemented: Read as ‘0’
bit 0 STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack full/underflow will cause Reset
0 = Stack full/underflow will not cause Reset
Legend:
r = Reserved bit, program as ‘0’
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
DS39689F-page 264
© 2009 Microchip Technology Inc.