PIC18F2221_1 Datasheet, PDF (82/402 Pages) Microchip Technology – Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2221/2321/4221/4321 FAMILY
7.2.2 TABLAT – TABLE LATCH REGISTER
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
7.2.3
TBLPTR – TABLE POINTER
REGISTER
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the device ID, the user ID and the Configuration bits.
The Table Pointer register, TBLPTR, is used by the
TBLRD and TBLWT instructions. These instructions can
update the TBLPTR in one of four ways based on the
table operation. These operations are shown in
Table 7-1. These operations on the TBLPTR only affect
the low-order 21 bits.
7.2.4 TABLE POINTER BOUNDARIES
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABLAT.
When the timed write to program memory begins (via
the WR bit), the 19 MSbs of the TBLPTR
(TBLPTR<21:3>) determine which program memory
block of 8 bytes is written to. The Table Pointer regis-
ter’s three LSBs (TBLPTR<2:0>) are ignored. For more
detail, see Section 7.5 “Writing to Flash Program
Memory”.
When an erase of program memory is executed, the
16 MSbs of the Table Pointer register (TBLPTR<21:6>)
point to the 64-byte block that will be erased. The Least
Significant bits (TBLPTR<5:0>) are ignored.
Figure 7-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
TABLE 7-1:
Example
TBLRD*
TBLWT*
TBLRD*+
TBLWT*+
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Operation on Table Pointer
TBLPTR is not modified
TBLPTR is incremented after the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented before the read/write
FIGURE 7-3:
TABLE POINTER BOUNDARIES BASED ON OPERATION
21
TBLPTRU 16 15
TBLPTRH
87
TBLPTRL
0
TABLE ERASE
TBLPTR<21:6>
TABLE WRITE
TBLPTR<21:3>
TABLE READ – TBLPTR<21:0>
DS39689F-page 82
© 2009 Microchip Technology Inc.