PIC18F2221_1 Datasheet, PDF (397/402 Pages) Microchip Technology – Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2221/2321/4221/4321 FAMILY
I²C Master Mode (7 or 10-Bit Transmission) ........... 202
I²C Master Mode (7-Bit Reception) .......................... 203
I²C Slave Mode (10-Bit Reception, SEN = 0,
ADMSK = 01001) ............................................. 187
I²C Slave Mode (10-Bit Reception, SEN = 0) .......... 188
I²C Slave Mode (10-Bit Reception, SEN = 1) .......... 193
I²C Slave Mode (10-Bit Transmission) ..................... 189
I²C Slave Mode (7-Bit Reception, SEN = 0,
ADMSK = 01011) ............................................. 185
I²C Slave Mode (7-Bit Reception, SEN = 0) ............ 184
I²C Slave Mode (7-Bit Reception, SEN = 1) ............ 192
I²C Slave Mode (7-Bit Transmission) ....................... 186
I²C Slave Mode General Call Address
Sequence (7 or 10-Bit Addressing Mode) ........ 194
I²C Stop Condition Receive or Transmit Mode ........ 204
Low-Voltage Detect Operation (VDIRMAG = 0) ...... 255
Master SSP I²C Bus Data ........................................ 367
Master SSP I²C Bus Start/Stop Bits ........................ 367
Parallel Slave Port (PIC18F4221/4321) ................... 360
Parallel Slave Port (PSP) Read ............................... 127
Parallel Slave Port (PSP) Write ............................... 127
PWM Auto-Shutdown (PRSEN = 0,
Auto-Restart Disabled) .................................... 164
PWM Auto-Shutdown (PRSEN = 1,
Auto-Restart Enabled) ..................................... 164
PWM Direction Change ........................................... 161
PWM Direction Change at Near
100% Duty Cycle ............................................. 161
PWM Output ............................................................ 150
Repeated Start Condition ......................................... 200
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST), Power-up Timer (PWRT) ........... 357
Send Break Character Sequence ............................ 227
Slave Synchronization ............................................. 173
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 53
SPI Mode (Master Mode) ......................................... 172
SPI Mode (Slave Mode, CKE = 0) ........................... 174
SPI Mode (Slave Mode, CKE = 1) ........................... 174
Synchronous Reception (Master Mode, SREN) ...... 230
Synchronous Transmission ...................................... 228
Synchronous Transmission (Through TXEN) .......... 229
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to VDD) ........................................... 53
Time-out Sequence on Power-up
(MCLR Not Tied to VDD, Case 1) ....................... 52
Time-out Sequence on Power-up
(MCLR Not Tied to VDD, Case 2) ....................... 52
Time-out Sequence on Power-up
(MCLR Tied to VDD, VDD Rise < TPWRT) ........... 52
Timer0 and Timer1 External Clock .......................... 358
Transition for Entry to Idle Mode ................................ 44
Transition for Entry to SEC_RUN Mode .................... 41
Transition for Entry to Sleep Mode ............................ 43
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ........................................ 271
Transition for Wake from Idle to Run Mode ............... 44
Transition for Wake from Sleep (HSPLL) ................... 43
Transition from RC_RUN Mode to PRI_RUN Mode .. 42
Transition from SEC_RUN Mode to
PRI_RUN Mode (HSPLL) .................................. 41
Transition to RC_RUN Mode ..................................... 42
Timing Diagrams and Specifications ............................... 354
Capture/Compare/PWM Requirements
(All CCP Modules) ........................................... 359
CLKO and I/O Requirements ................................... 356
EUSART Synchronous Receive Requirements ....... 369
EUSART Synchronous Transmission Requirements ....
369
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 361
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 362
Example SPI Mode Requirements
(Slave Mode, CKE = 0) .................................... 363
Example SPI Mode Requirements
(Slave Mode, CKE = 1) .................................... 364
External Clock Requirements .................................. 354
I²C Bus Data Requirements (Slave Mode) .............. 366
I²C Bus Start/Stop Requirements (Slave Mode) ..... 365
Master SSP I²C Bus Data Requirements ................ 368
Master SSP I²C Bus Start/Stop Bits
Requirements .................................................. 367
Parallel Slave Port Requirements
(PIC18F4221/4321) ......................................... 360
PLL Clock ................................................................ 355
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and
Brown-out Reset Requirements ...................... 357
Timer0 and Timer1 External Clock
Requirements .................................................. 358
Top-of-Stack Access .......................................................... 60
TRISE Register
PSPMODE Bit ......................................................... 120
TSTFSZ ........................................................................... 319
Two-Speed Start-up ................................................. 259, 271
Two-Word Instructions
Example Cases ......................................................... 64
TXSTA Register
BRGH Bit ................................................................. 215
V
Voltage Reference Specifications .................................... 350
W
Watchdog Timer (WDT) ........................................... 259, 269
Associated Registers ............................................... 270
Control Register ....................................................... 269
During Oscillator Failure .......................................... 272
Programming Considerations .................................. 269
WCOL ...................................................... 199, 200, 201, 204
WCOL Status Flag ................................... 199, 200, 201, 204
WWW Address ................................................................ 399
WWW, On-Line Support ...................................................... 8
X
XORLW ........................................................................... 319
XORWF ........................................................................... 320
© 2009 Microchip Technology Inc.
DS39689F-page 397