PIC18F2221_1 Datasheet, PDF (71/402 Pages) Microchip Technology – Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2221/2321/4221/4321 FAMILY
TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2221/2321/4221/4321) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details on
POR, BOR page:
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EEADR
EEDATA
EECON2
EECON1
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
TRISE⁽²⁾
TRISD⁽²⁾
TRISC
TRISB
TRISA
LATE⁽²⁾
LATD⁽²⁾
LATC
LATB
LATA
PORTE
PORTD⁽²⁾
PORTC
PORTB
PORTA
Legend:
Note 1:
2:
3:
4:
5:
6:
EUSART Baud Rate Generator Register High Byte
0000 0000 57, 216
EUSART Baud Rate Generator Register Low Byte
0000 0000 57, 216
EUSART Receive Register
0000 0000 57, 224
EUSART Transmit Register
0000 0000 57, 221
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D 0000 0010 57, 212
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x 57, 213
EEPROM Address Register
0000 0000 57, 80, 89
EEPROM Data Register
0000 0000 57, 80, 89
EEPROM Control Register 2 (not a physical register)
0000 0000 57, 80, 89
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
xx-0 x000 57, 81, 90
OSCFIP
CMIP
—
EEIP
BCLIP
HLVDIP
TMR3IP
CCP2IP 11-1 1111 58, 107
OSCFIF
CMIF
—
EEIF
BCLIF
HLVDIF
TMR3IF
CCP2IF 00-0 0000 58, 103
OSCFIE
PSPIP⁽²⁾
PSPIF⁽²⁾
PSPIE⁽²⁾
INTSRC
CMIE
ADIP
ADIF
ADIE
PLLEN⁽³⁾
—
RCIP
RCIF
RCIE
—
EEIE
TXIP
TXIF
TXIE
TUN4
BCLIE
SSPIP
SSPIF
SSPIE
TUN3
HLVDIE
CCP1IP
CCP1IF
CCP1IE
TUN2
TMR3IE
TMR2IP
TMR2IF
TMR2IE
TUN1
CCP2IE
TMR1IP
TMR1IF
TMR1IE
TUN0
00-0 0000
1111 1111
0000 0000
0000 0000
00-0 0000
58, 105
58, 106
58, 102
58, 104
33, 58
IBF
OBF
IBOV PSPMODE
—
TRISE2
TRISE1
TRISE0 0000 -111 58, 124
PORTD Data Direction Control Register
1111 1111 58, 120
PORTC Data Direction Control Register
1111 1111 58, 117
PORTB Data Direction Control Register
TRISA7⁽⁵⁾ TRISA6⁽⁵⁾ PORTA Data Direction Control Register
1111 1111 58, 114
1111 1111 58, 111
—
—
—
—
—
PORTE Data Latch Register
(Read and Write to Data Latch)
---- -xxx 58, 123
PORTD Data Latch Register (Read and Write to Data Latch)
xxxx xxxx 58, 120
PORTC Data Latch Register (Read and Write to Data Latch)
xxxx xxxx 58, 117
PORTB Data Latch Register (Read and Write to Data Latch)
LATA7⁽⁵⁾ LATA6⁽⁵⁾ PORTA Data Latch Register (Read and Write to Data Latch)
—
—
—
—
RE3⁽⁴⁾
RE2⁽²⁾
RE1⁽²⁾
RE0⁽²⁾
xxxx xxxx
xxxx xxxx
---- xxxx
58, 114
58, 111
58, 123
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0 xxxx xxxx 58, 120
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0 xxxx xxxx 58, 117
RB7
RA7⁽⁵⁾
RB6
RA6⁽⁵⁾
RB5
RA5
RB4
RA4
RB3
RA3
RB2
RA2
RB1
RA1
RB0 xxxx xxxx 58, 114
RA0 xx0x 0000 58, 111
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See
Section 5.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.6.4 “PLL in
INTOSC Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
Bit 7 and bit 6 are cleared by user software or by a POR.
© 2009 Microchip Technology Inc.
DS39689F-page 71