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| PIC18F2221_1 Datasheet, PDF (149/402 Pages) Microchip Technology – Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology | |||
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PIC18F2221/2321/4221/4321 FAMILY
TABLE 16-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE TMR0IF INT0IF
RBIF
55
RCON
PIR1
PIE1
IPR1
IPEN
PSPIF(2)
PSPIE(2)
PSPIP(2)
SBOREN(1)
ADIF
ADIE
ADIP
â
RCIF
RCIE
RCIP
RI
TO
PD
POR
BOR
54
TXIF
SSPIF CCP1IF TMR2IF TMR1IF
58
TXIE
SSPIE CCP1IE TMR2IE TMR1IE
58
TXIP
SSPIP CCP1IP TMR2IP TMR1IP
58
PIR2
OSCFIF CMIF
â
EEIF
BCLIF HLVDIF TMR3IF CCP2IF
58
PIE2
OSCFIE CMIE
â
EEIE
BCLIE HLVDIE TMR3IE CCP2IE
58
IPR2
OSCFIP CMIP
â
EEIP
BCLIP HLVDIP TMR3IP CCP2IP
58
TRISB PORTB Data Direction Register
58
TRISC PORTC Data Direction Register
58
TMR1L Timer1 Register Low Byte
56
TMR1H Timer1 Register High Byte
56
T1CON
RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 56
TMR3H Timer3 Register High Byte
57
TMR3L Timer3 Register Low Byte
57
T3CON
RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 57
CCPR1L Capture/Compare/PWM Register 1 Low Byte
57
CCPR1H Capture/Compare/PWM Register 1 High Byte
57
CCP1CON P1M1(2) P1M0(2) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 57
CCPR2L Capture/Compare/PWM Register 2 Low Byte
57
CCPR2H Capture/Compare/PWM Register 2 High Byte
57
CCP2CON â
â
DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 57
Legend:
Note 1:
2:
â = unimplemented, read as â0â. Shaded cells are not used by Capture/Compare, Timer1 or Timer3.
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, it is disabled
and reads as â0â. See Section 5.4 âBrown-out Reset (BOR)â.
These bits are unimplemented on 28-pin devices and read as â0â.
© 2009 Microchip Technology Inc.
DS39689F-page 149
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