PIC16F870_13 Datasheet, PDF (82/172 Pages) Microchip Technology – 28/40-Pin, 8-Bit CMOS FLASH Microcontrollers

PIC16F870/871
10.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 10-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD), see Figure 10-2. The maximum recom-
mended impedance for analog sources is 10 k. As
the impedance is decreased, the acquisition time may
be decreased. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
To calculate the minimum acquisition time,
Equation 10-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
To calculate the minimum acquisition time, TACQ, see
the PIC^® Mid-Range MCU Family Reference Manual
(DS33023).
EQUATION 10-1: ACQUISITION TIME
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
TC
TACQ
= TAMP + TC + TCOFF
= 2 s + TC + [(Temperature – 25°C)(0.05 s/°C)]
= CHOLD (RIC + RSS + RS) In(1/2047)
= - 120 pF (1 k + 7 k + 10 k) In(0.0004885)
= 16.47 s
= 2 s + 16.47 s + [(50°C – 25C)(0.05 s/C)
= 19.72 s
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
4: After a conversion has completed, a 2.0 TAD delay must complete before acquisition can begin again.
During this time, the holding capacitor is not connected to the selected A/D input channel.
FIGURE 10-2:
ANALOG INPUT MODEL
RS ^ANx
VDD
VT = 0.6V
VA
CPIN
5 pF
VT = 0.6V
Sampling
Switch
RIC  1k SS RSS
I LEAKAGE
± 500 nA
CHOLD
= DAC capacitance
= 120 pF
VSS
Legend
CPIN
= input capacitance
VT
= threshold voltage
I LEAKAGE = leakage current at the pin due to
various junctions
RIC
SS
CHOLD
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
6V
5V
VDD 4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch
(k)
DS30569C-page 82
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