PIC16F870_13 Datasheet, PDF (31/172 Pages) Microchip Technology – 28/40-Pin, 8-Bit CMOS FLASH Microcontrollers

At the completion of the write cycle, the WR bit is
cleared and the EEIF interrupt flag bit is set. (EEIF
must be cleared by firmware.) Since the microcontroller
does not execute instructions during the write cycle, the
firmware does not necessarily have to check either
EEIF, or WR, to determine if the write had finished.
EXAMPLE 3-4: FLASH PROGRAM WRITE
BSF
BCF
MOVF
MOVWF
MOVF
MOVWF
MOVF
MOVWF
MOVF
MOVWF
BSF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
BSF
STATUS, RP1 ;
STATUS, RP0 ;Bank 2
ADDRL, W
;Write address
EEADR
;of desired
ADDRH, W
;program memory
EEADRH
;location
VALUEL, W
;Write value to
EEDATA
;program at
VALUEH, W
;desired memory
EEDATH
;location
STATUS, RP0 ;Bank 3
EECON1, EEPGD ;Point to Program memory
EECON1, WREN ;Enable writes
;Only disable interrupts
INTCON, GIE ;if already enabled,
;otherwise discard
0x55
;Write 55h to
EECON2
;EECON2
0xAA
;Write AAh to
EECON2
;EECON2
EECON1, WR ;Start write operation
;Two NOPs to allow micro
;to setup for write
;Only enable interrupts
INTCON, GIE ;if using interrupts,
;otherwise discard
BCF EECON1, WREN ;Disable writes
3.7 Write Verify
The PIC16F870/871 devices do not automatically ver-
ify the value written during a write operation. Depend-
ing on the application, good programming practice may
dictate that the value written to memory be verified
against the original value. This should be used in appli-
cations where excessive writes can stress bits near the
specified endurance limits.
PIC16F870/871
3.8 Protection Against Spurious
Writes
There are conditions when the device may not want to
write to the EEPROM data memory or FLASH program
memory. To protect against these spurious write condi-
tions, various mechanisms have been built into the
PIC16F870/871 devices. On power-up, the WREN bit
is cleared and the Power-up Timer (if enabled)
prevents writes.
The write initiate sequence and the WREN bit together,
help prevent any accidental writes during brown-out,
power glitches, or firmware malfunction.
3.9 Operation While Code Protected
The PIC16F870/871 devices have two code protect
mechanisms, one bit for EEPROM data memory and
two bits for FLASH program memory. Data can be read
and written to the EEPROM data memory, regardless
of the state of the code protection bit, CPD. When code
protection is enabled and CPD cleared, external
access via ICSP is disabled, regardless of the state of
the program memory code protect bits. This prevents
the contents of EEPROM data memory from being read
out of the device.
The state of the program memory code protect bits,
CP0 and CP1, do not affect the execution of instruc-
tions out of program memory. The PIC16F870/871
devices can always read the values in program mem-
ory, regardless of the state of the code protect bits.
However, the state of the code protect bits and the
WRT bit will have different effects on writing to program
memory. Table 4-1 shows the effect of the code protect
bits and the WRT bit on program memory.
Once code protection has been enabled for either
EEPROM data memory or FLASH program memory,
only a full erase of the entire device will disable code
protection.
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DS30569C-page 31