PIC16F870_13 Datasheet, PDF (71/172 Pages) Microchip Technology – 28/40-Pin, 8-Bit CMOS FLASH Microcontrollers

PIC16F870/871
FIGURE 9-7:
RC7/RX/DT (pin)
Load RSR
Read
ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
START
bit bit0 bit1
START
bit8 STOP bit bit0
bit
bit8 STOP
bit
Bit8 = 0, Data Byte
Bit8 = 1, Address Byte
Word 1
RCREG
RCIF
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer)
because ADDEN = 1.
FIGURE 9-8:
RC7/RX/DT (pin)
Load RSR
Read
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
START
bit _{bit0 bit1}
START
bit8 STOP bit bit0
bit
bit8 STOP
bit
Bit8 = 1, Address Byte
Bit8 = 0, Data Byte
Word 1
RCREG
RCIF
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer)
because ADDEN was not updated and still = 0.
TABLE 9-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Address Name
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
RESETS
0Bh, 8Bh, INTCON
10Bh,18Bh
0Ch
PIR1
GIE
PSPIF⁽¹⁾
PEIE
ADIF
T0IE
RCIF
INTE
TXIF
RBIE T0IF INTF R0IF 0000 000x 0000 000u
— CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
18h
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah
RCREG USART Receive Register
0000 0000 0000 0000
8Ch
PIE1
PSPIE⁽¹⁾ ADIE RCIE TXIE
— CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
98h
TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
 2000-2013 Microchip Technology Inc.
DS30569C-page 71