PIC16F870_13 Datasheet, PDF(42/172 Page) Microchip Technology – 28/40-Pin, 8-Bit CMOS FLASH Microcontrollers

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PIC16F870_13 Datasheet, PDF (42/172 Pages) Microchip Technology – 28/40-Pin, 8-Bit CMOS FLASH Microcontrollers

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PIC16F870/871

4.6 Parallel Slave Port

The Parallel Slave Port is not implemented on the

PIC16F870.

PORTD operates as an 8-bit wide Parallel Slave Port or

microprocessor port when control bit PSPMODE

(TRISE<4>) is set. In Slave mode, it is asynchronously

readable and writable by the external world through RD

control input pin RE0/RD and WR control input pin

RE1/WR.

It can directly interface to an 8-bit microprocessor data

bus. The external microprocessor can read or write the

PORTD latch as an 8-bit latch. Setting bit PSPMODE

enables port pin RE0/RD to be the RD input, RE1/WR

to be the WR input and RE2/CS to be the CS (chip

select) input. For this functionality, the corresponding

data direction bits of the TRISE register (TRISE<2:0>)

must be configured as inputs (set). The A/D port config-

uration bits PCFG3:PCFG0 (ADCON1<3:0>) must be

set to configure pins RE2:RE0 as digital I/O.

There are actually two 8-bit latches. One for data out-

put and one for data input. The user writes 8-bit data to

the PORTD data latch and reads data from the port pin

latch (note that they have the same address). In this

mode, the TRISD register is ignored, since the

microprocessor is controlling the direction of data flow.

A write to the PSP occurs when both the CS and WR

lines are first detected low. When either the CS or WR

lines become high (level triggered), the Input Buffer Full

(IBF) status flag bit (TRISE<7>) is set on the Q4 clock

cycle, following the next Q2 cycle, to signal the write is

complete (Figure 4-9). The interrupt flag bit, PSPIF

(PIR1<7>), is also set on the same Q4 clock cycle. IBF

can only be cleared by reading the PORTD input latch.

The Input Buffer Overflow (IBOV) status flag bit

(TRISE<5>) is set if a second write to the PSP is

attempted when the previous byte has not been read

out of the buffer.

A read from the PSP occurs when both the CS and RD

lines are first detected low. The Output Buffer Full

(OBF) status flag bit (TRISE<6>) is cleared immedi-

ately (Figure 4-10), indicating that the PORTD latch is

waiting to be read by the external bus. When either the

CS or RD pin becomes high (level triggered), the inter-

rupt flag bit PSPIF is set on the Q4 clock cycle, follow-

ing the next Q2 cycle, indicating that the read is

complete. OBF remains low until data is written to

PORTD by the user firmware.

When not in PSP mode, the IBF and OBF bits are held

clear. However, if flag bit IBOV was previously set, it

must be cleared in firmware.

An interrupt is generated and latched into flag bit

PSPIF when a read or write operation is completed.

PSPIF must be cleared by the user in firmware and the

interrupt can be disabled by clearing the interrupt

enable bit PSPIE (PIE1<7>).

FIGURE 4-8:

PORTD AND PORTE

BLOCK DIAGRAM

(PARALLEL SLAVE PORT)

Data Bus

Port

ENEN

Port

One bit of PORTD

Set Interrupt Flag

PSPIF (PIR1<7>)

RDx

TTL

Read

TTL

Chip Select

TTL

Write

TTL

Note: I/O pin has protection diodes to VDD and VSS.

DS30569C-page 42

ï£ 2000-2013 Microchip Technology Inc.

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