PIC16F870_13 Datasheet, PDF (15/172 Pages) Microchip Technology – 28/40-Pin, 8-Bit CMOS FLASH Microcontrollers

PIC16F870/871
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name
Bit 7
Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
RESETS⁽²⁾
Bank 2
100h⁽⁴⁾ INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
101h
TMR0
Timer0 Module’s Register
xxxx xxxx uuuu uuuu
102h⁽⁴⁾ PCL
Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
103h⁽⁴⁾ STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu
104h⁽⁴⁾ FSR
Indirect Data Memory Address Pointer
xxxx xxxx uuuu uuuu
105h
—
Unimplemented
—
—
106h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx uuuu uuuu
107h
—
Unimplemented
—
—
108h
—
Unimplemented
—
—
109h
10Ah^(1,4)
10Bh⁽⁴⁾
—
PCLATH
INTCON
Unimplemented
—
—
GIE
PEIE
—
T0IE
Write Buffer for the upper 5 bits of the Program Counter
INTE
RBIE
T0IF
INTF
RBIF
—
—
---0 0000 ---0 0000
0000 000x 0000 000u
10Ch
EEDATA
EEPROM Data Register
xxxx xxxx uuuu uuuu
10Dh
EEADR
EEPROM Address Register
xxxx xxxx uuuu uuuu
10Eh
EEDATH
—
— EEPROM Data Register High Byte
xxxx xxxx uuuu uuuu
10Fh
EEADRH
—
—
— EEPROM Address Register High Byte
xxxx xxxx uuuu uuuu
Bank 3
180h⁽⁴⁾ INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
181h
OPTION_REG RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0 1111 1111 1111 1111
182h⁽⁴⁾ PCL
Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
183h⁽⁴⁾ STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu
184h⁽⁴⁾ FSR
Indirect Data Memory Address Pointer
xxxx xxxx uuuu uuuu
185h
—
Unimplemented
—
—
186h
TRISB
PORTB Data Direction Register
1111 1111 1111 1111
187h
—
Unimplemented
—
—
188h
—
Unimplemented
—
—
189h
18Ah^(1,4)
18Bh⁽⁴⁾
—
PCLATH
INTCON
Unimplemented
—
—
GIE
PEIE
—
T0IE
Write Buffer for the upper 5 bits of the Program Counter
INTE
RBIE
T0IF
INTF
RBIF
—
—
---0 0000 ---0 0000
0000 000x 0000 000u
18Ch
EECON1
EEPGD
—
—
—
WRERR WREN
WR
RD x--- x000 x--- u000
18Dh
EECON2
EEPROM Control Register2 (not a physical register)
---- ---- ---- ----
18Eh
—
Reserved maintain clear
0000 0000 0000 0000
18Fh
—
Reserved maintain clear
0000 0000 0000 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
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DS30569C-page 15