PIC16F870_13 Datasheet, PDF(14/172 Page) Microchip Technology – 28/40-Pin, 8-Bit CMOS FLASH Microcontrollers

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PIC16F870_13 Datasheet, PDF (14/172 Pages) Microchip Technology – 28/40-Pin, 8-Bit CMOS FLASH Microcontrollers

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PIC16F870/871

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name

Bit 7 Bit 6 Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR, BOR

Value on

all other

RESETS(2)

Bank 1

80h(4)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

81h

OPTION_REG RBPU INTEDG T0CS

T0SE

PSA

PS2

PS1

PS0 1111 1111 1111 1111

82h(4)

PCL

Program Counter's (PC) Least Significant Byte

0000 0000 0000 0000

83h(4)

STATUS

IRP

RP1

RP0

0001 1xxx 000q quuu

84h(4)

FSR

Indirect Data Memory Address Pointer

xxxx xxxx uuuu uuuu

85h

TRISA

â PORTA Data Direction Register

--11 1111 --11 1111

86h

TRISB

PORTB Data Direction Register

1111 1111 1111 1111

87h

88h(5)

89h(5)

8Ah(1,4)

8Bh(4)

8Ch

TRISC

TRISD

TRISE

PCLATH

INTCON

PIE1

PORTC Data Direction Register

PORTD Data Direction Register

IBF

OBF

IBOV

GIE

PSPIE(3)

PEIE

ADIE

T0IE

RCIE

1111 1111 1111 1111

PSPMODE

PORTE Data Direction Bits

0000 -111 0000 -111

Write Buffer for the upper 5 bits of the Program Counter

---0 0000 ---0 0000

INTE

RBIE

T0IF

INTF

RBIF 0000 000x 0000 000u

TXIE

CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

8Dh

PIE2

EEIE

â ---0 ---- ---0 ----

8Eh

PCON

POR

BOR ---- --qq ---- --uu

8Fh

Unimplemented

90h

Unimplemented

91h

Unimplemented

92h

PR2

Timer2 Period Register

1111 1111 1111 1111

93h

Unimplemented

94h

Unimplemented

95h

Unimplemented

96h

Unimplemented

97h

Unimplemented

98h

TXSTA

CSRC

TX9

TXEN

SYNC

BRGH

TRMT

TX9D 0000 -010 0000 -010

99h

SPBRG

Baud Rate Generator Register

0000 0000 0000 0000

9Ah

Unimplemented

9Bh

Unimplemented

9Ch

Unimplemented

9Dh

Unimplemented

9Eh

ADRESL

A/D Result Register Low Byte

xxxx xxxx uuuu uuuu

9Fh

ADCON1

ADFM

PCFG3 PCFG2 PCFG1 PCFG0 0--- 0000 0--- 0000

Legend:

Note 1:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.

Shaded locations are unimplemented, read as â0â.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter.

Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.

Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.

These registers can be addressed from any bank.

PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as â0â.

DS30569C-page 14

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