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PIC16F870_13 Datasheet, PDF (11/172 Pages) Microchip Technology – 28/40-Pin, 8-Bit CMOS FLASH Microcontrollers
2.0 MEMORY ORGANIZATION
The PIC16F870/871 devices have three memory
blocks. The Program Memory and Data Memory have
separate buses, so that concurrent access can occur,
and is detailed in this section. The EEPROM data
memory block is detailed in Section 3.0.
Additional information on device memory may be found
in the PICmicroTM Mid-Range MCU Family Reference
Manual (DS33023).
2.1 Program Memory Organization
The PIC16F870/871 devices have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. The PIC16F870/871 devices have
2K x 14 words of FLASH program memory. Accessing
a location above the physically implemented address
will cause a wraparound.
The RESET vector is at 0000h and the interrupt vector
is at 0004h.
FIGURE 2-1:
PIC16F870/871 PROGRAM
MEMORY MAP AND STACK
PC<12:0>
CALL, RETURN
13
RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 8
RESET Vector
0000h
PIC16F870/871
2.2 Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (STATUS<6>)
and RP0 (STATUS<5>) are the bank select bits.
RP<1:0>
00
01
10
11
Bank
0
1
2
3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some “high use” Special Function
Registers from one bank may be mirrored in another
bank for code reduction and quicker access.
Note: EEPROM Data Memory description can
be found in Section 3.0 of this Data Sheet.
2.2.1
GENERAL PURPOSE REGISTER
FILE
The register file can be accessed either directly, or
indirectly through the File Select Register FSR.
On-Chip
Program
Memory
Interrupt Vector
Page 0
0004h
0005h
07FFh
0800h
1FFFh
 2000-2013 Microchip Technology Inc.
DS30569C-page 11