PIC18F23K20 Datasheet, PDF (81/420 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2XK20/4XK20
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2XK20/4XK20) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EEADR
EEADRH
EEDATA
EECON2
EECON1
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
TRISE⁽²⁾
TRISD⁽²⁾
TRISC
TRISB
TRISA
LATE⁽²⁾
LATD⁽²⁾
LATC
LATB
LATA
PORTE
PORTD⁽²⁾
PORTC
PORTB
PORTA
ANSELH⁽⁶⁾
ANSEL
IOCB
WPUB
CM1CON0
CM2CON0
CM2CON1
SLRCON
SSPMSK
Legend:
Note 1:
2:
3:
4:
5:
6:
EUSART Baud Rate Generator Register, High Byte
0000 0000 59, 227
EUSART Baud Rate Generator Register, Low Byte
0000 0000 59, 227
EUSART Receive Register
0000 0000 59, 228
EUSART Transmit Register
0000 0000 59, 227
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D 0000 0010 59, 236
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x 59, 237
EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 59, 88, 97
—
—
—
—
—
—
EEADR9 EEADR8 ---- --00 59, 88, 97
EEPROM Data Register
0000 0000 59, 88, 97
EEPROM Control Register 2 (not a physical register)
0000 0000 59, 88, 97
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
xx-0 x000 59, 89, 97
OSCFIP
C1IP
C2IP
EEIP
BCLIP
HLVDIP
TMR3IP
CCP2IP 1111 1111 60, 113
OSCFIF
C1IF
C2IF
EEIF
BCLIF
HLVDIF
TMR3IF
CCP2IF 0000 0000 60, 109
OSCFIE
PSPIP⁽²⁾
PSPIF⁽²⁾
PSPIE⁽²⁾
INTSRC
C1IE
ADIP
ADIF
ADIE
PLLEN⁽³⁾
C2IE
RCIP
RCIF
RCIE
TUN5
EEIE
TXIP
TXIF
TXIE
TUN4
BCLIE
SSPIP
SSPIF
SSPIE
TUN3
HLVDIE
CCP1IP
CCP1IF
CCP1IE
TUN2
TMR3IE
TMR2IP
TMR2IF
TMR2IE
TUN1
CCP2IE
TMR1IP
TMR1IF
TMR1IE
TUN0
0000 0000
1111 1111
0000 0000
0000 0000
0q00 0000
60, 111
60, 112
60, 108
60, 110
31, 60
IBF
OBF
IBOV PSPMODE
—
TRISE2
TRISE1
TRISE0 0000 -111 60, 130
PORTD Data Direction Control Register
1111 1111 60, 126
PORTC Data Direction Control Register
1111 1111 60, 123
PORTB Data Direction Control Register
TRISA7⁽⁵⁾ TRISA6⁽⁵⁾ Data Direction Control Register for PORTA
1111 1111 60, 120
1111 1111 60, 117
—
—
—
—
—
PORTE Data Latch Register
---- -xxx 60, 129
(Read and Write to Data Latch)
PORTD Data Latch Register (Read and Write to Data Latch)
xxxx xxxx 60, 126
PORTC Data Latch Register (Read and Write to Data Latch)
xxxx xxxx 60, 123
PORTB Data Latch Register (Read and Write to Data Latch)
LATA7⁽⁵⁾ LATA6⁽⁵⁾ PORTA Data Latch Register (Read and Write to Data Latch)
—
—
—
—
RE3⁽⁴⁾
RE2⁽²⁾
RE1⁽²⁾
RE0⁽²⁾
xxxx xxxx
xxxx xxxx
---- x000
60, 120
60, 117
60, 129
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0 xxxx xxxx 60, 126
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0 xxxx xxxx 60, 123
RB7
RA7⁽⁵⁾
RB6
RA6⁽⁵⁾
RB5
RA5
RB4
RA4
RB3
RA3
RB2
RA2
RB1
RA1
RB0 xxx0 0000 60, 120
RA0 xx0x 0000 60, 117
—
ANS7⁽²⁾
—
ANS6⁽²⁾
—
ANS5⁽²⁾
ANS12
ANS4
ANS11
ANS3
ANS10
ANS2
ANS9
ANS1
ANS8
ANS0
---1 1111 60, 133
1111 1111 60, 132
IOCB7
IOCB6
IOCB5
IOCB4
—
—
—
—
0000 ---- 60, 120
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0 1111 1111 60, 120
C1ON
C1OUT
C1OE
C1POL
C1SP
C1R
C1CH1
C1CH0 0000 0000 60, 274
C2ON
C2OUT
C2OE
C2POL
C2SP
C2R
C2CH1
C2CH0 0000 0000 60, 275
MC1OUT MC2OUT C1RSEL C2RSEL
—
—
—
—
0000 ---- 61, 277
—
—
—
SLRE
SLRD
SLRC
SLRB
SLRA ---1 1111 61, 134
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0 1111 1111 61, 204
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section 2.6.2 “PLL in
HFINTOSC Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RE3 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 79