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PIC18F23K20 Datasheet, PDF (187/420 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology | |||
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17.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
17.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
⢠Serial Peripheral Interface (SPI)
⢠Inter-Integrated Circuit (I2C)
- Full Master mode
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
⢠Master mode
⢠Multi-Master mode
⢠Slave mode
17.2 Control Registers
The MSSP module has seven associated registers.
These include:
⢠SSPSTA â STATUS register
⢠SSPCON1 â First Control register
⢠SSPCON2 â Second Control register
⢠SSPBUF â Transmit/Receive buffer
⢠SSPSR â Shift register (not directly accessible)
⢠SSPADD â Address register
⢠SSPMSK â Address Mask register
The use of these registers and their individual Configu-
ration bits differ significantly depending on whether the
MSSP module is operated in SPI or I2C mode.
Additional details are provided under the individual
sections.
PIC18F2XK20/4XK20
17.3 SPI Mode
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish
communication, typically three pins are used:
⢠Serial Data Out â SDO
⢠Serial Data In â SDI/SDA
⢠Serial Clock â SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
⢠Slave Select â SS
Figure 17-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 17-1:
MSSP BLOCK DIAGRAM
(SPI MODE)
Internal
Data Bus
Read
Write
SSPBUF Reg
SDI/SDA
SDO
SSPSR Reg
bit 0
Shift
Clock
SS
SCK/SCL
SS Control
Enable
Edge
Select
2
Clock Select
SSPM<3:0>
SMP:CKE 4
2
( ) TMR2 Output
2
Edge
Select
Prescaler TOSC
4, 16, 64
Data to TX/RX in SSPSR
TRIS bit
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 185
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