PIC18F23K20 Datasheet, PDF (80/420 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2XK20/4XK20
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2XK20/4XK20) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
TMR0H
TMR0L
T0CON
OSCCON
HLVDCON
WDTCON
RCON
Timer0 Register, High Byte
Timer0 Register, Low Byte
TMR0ON T08BIT
IDLEN
IRCF2
VDIRMAG
—
—
—
IPEN
SBOREN⁽¹⁾
T0CS
IRCF1
IRVST
—
—
TMR1H
TMR1L
Timer1 Register, High Byte
Timer1 Register, Low Bytes
T0SE
IRCF0
HLVDEN
—
RI
PSA
OSTS
HLVDL3
—
TO
T0PS2
IOFS
HLVDL2
—
PD
T0PS1
SCS1
HLVDL1
—
POR
0000 0000 58, 139
xxxx xxxx 58, 139
T0PS0 1111 1111 58, 137
SCS0 0011 qq00 27, 58
HLVDL0 0-00 0101 58, 283
SWDTEN --- ---0 58, 299
BOR
0q-1 11q0 49, 56,
114
xxxx xxxx 58, 146
xxxx xxxx 58, 146
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 58, 141
Timer2 Register
0000 0000 58, 148
Timer2 Period Register
1111 1111 58, 148
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 58, 147
SSP Receive Buffer/Transmit Register
SSP Address Register in I²C™ Slave Mode. SSP Baud Rate Reload Register in I²C Master Mode.
xxxx xxxx 58, 193,
194
0000 0000 58, 194
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 58, 187,
196
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0 0000 0000 58, 187,
196
GCEN ACKSTAT ACKDT
ACKEN
RCEN
PEN
RSEN
SEN 0000 0000 58, 197
A/D Result Register, High Byte
xxxx xxxx 59, 267
A/D Result Register, Low Byte
xxxx xxxx 59, 267
ADCON0
—
—
CHS3
CHS2
CHS1
CHS0 GO/DONE ADON --00 0000 59, 261
ADCON1
—
—
VCFG1
VCFG0
—
—
—
—
--00 ---- 59, 262
ADCON2
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0 0-00 0000 59, 263
CCPR1H Capture/Compare/PWM Register 1, High Byte
xxxx xxxx 59, 154
CCPR1L Capture/Compare/PWM Register 1, Low Byte
xxxx xxxx 59, 154
CCP1CON
P1M1
P1M0
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 59, 165
CCPR2H Capture/Compare/PWM Register 2, High Byte
xxxx xxxx 59, 154
CCPR2L Capture/Compare/PWM Register 2, Low Byte
xxxx xxxx 59, 154
CCP2CON
—
—
DC2B1
DC2B0
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 59, 153
PSTRCON
—
—
—
STRSYNC STRD
STRC
STRB
STRA ---0 0001 59, 179
BAUDCTL
ABDOVF
RCIDL
DTRXP
CKTXP
BRG16
—
WUE
ABDEN 0100 0-00 59, 238
PWM1CON PRSEN
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0 0000 0000 59, 178
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 59, 175
CVRCON
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0 0000 0000 59, 281
CVRCON2
FVREN
FVRST
—
—
—
—
—
—
00-- ---- 59, 282
TMR3H
Timer3 Register, High Byte
xxxx xxxx 59, 151
TMR3L
Timer3 Register, Low Byte
xxxx xxxx 59, 151
T3CON
RD16
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 59, 149
Legend:
Note 1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section 2.6.2 “PLL in
HFINTOSC Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RE3 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
DS41303B-page 78
Advance Information
© 2007 Microchip Technology Inc.