PIC18F23K20 Datasheet, PDF (410/420 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2XK20/4XK20
Synchronous Mode .......................................... 243
Interrupts
Asychronous Receive ...................................... 229
Asychronous Transmit ..................................... 225
Synchronous Master Mode .............................. 243, 247
Associated Registers, Receive ........................ 246
Associated Registers, Transmit ............... 244, 247
Reception ......................................................... 245
Transmission .................................................... 243
Synchronous Slave Mode
Associated Registers, Receive ........................ 248
Reception ......................................................... 248
Transmission .................................................... 247
Extended Instruction Set
ADDFSR .................................................................. 342
ADDULNK ................................................................ 342
and Using MPLAB Tools .......................................... 348
CALLW ..................................................................... 343
Considerations for Use ............................................ 346
MOVSF .................................................................... 343
MOVSS .................................................................... 344
PUSHL ..................................................................... 344
SUBFSR .................................................................. 345
SUBULNK ................................................................ 345
Syntax ...................................................................... 341
F
Fail-Safe Clock Monitor .............................................. 38, 283
Fail-Safe Condition Clearing ...................................... 38
Fail-Safe Detection .................................................... 38
Fail-Safe Operation .................................................... 38
Reset or Wake-up from Sleep .................................... 38
Fast Register Stack ............................................................ 66
Firmware Instructions ....................................................... 299
Flash Program Memory ...................................................... 85
Associated Registers ................................................. 93
Control Registers ....................................................... 86
EECON1 and EECON2 ..................................... 86
TABLAT (Table Latch) Register ......................... 88
TBLPTR (Table Pointer) Register ...................... 88
Erase Sequence ........................................................ 90
Erasing ....................................................................... 90
Operation During Code-Protect ................................. 93
Reading ...................................................................... 89
Table Pointer
Boundaries Based on Operation ........................ 88
Table Pointer Boundaries .......................................... 88
Table Reads and Table Writes .................................. 85
Write Sequence ......................................................... 91
Writing To ................................................................... 91
Protection Against Spurious Writes ................... 93
Unexpected Termination .................................... 93
Write Verify ........................................................ 93
G
General Call Address Support ......................................... 207
GOTO ............................................................................... 320
H
Hardware Multiplier ............................................................ 99
Introduction ................................................................ 99
Operation ................................................................... 99
Performance Comparison .......................................... 99
High/Low-Voltage Detect ................................................. 277
Applications .............................................................. 281
Associated Registers ............................................... 281
Characteristics ......................................................... 366
Current Consumption ............................................... 279
Effects of a Reset .................................................... 281
Operation ................................................................. 278
During Sleep .................................................... 281
Setup ....................................................................... 279
Start-up Time ........................................................... 279
Typical Application ................................................... 281
HLVD. See High/Low-Voltage Detect. ............................. 277
HLVDCON Register ......................................................... 277
I
I/O Ports ........................................................................... 115
I²C Mode (MSSP)
Acknowledge Sequence Timing .............................. 217
Baud Rate Generator .............................................. 210
Bus Collision
During a Repeated Start Condition .................. 221
During a Stop Condition .................................. 222
Clock Arbitration ...................................................... 211
Clock Stretching ....................................................... 203
10-Bit Slave Receive Mode (SEN = 1) ............ 203
10-Bit Slave Transmit Mode ............................ 203
7-Bit Slave Receive Mode (SEN = 1) .............. 203
7-Bit Slave Transmit Mode .............................. 203
Clock Synchronization and the CKP bit (SEN = 1) .. 204
Effects of a Reset .................................................... 218
General Call Address Support ................................. 207
I²C Clock Rate w/BRG ............................................. 210
Master Mode ............................................................ 208
Operation ......................................................... 209
Reception ........................................................ 214
Repeated Start Condition Timing .................... 213
Start Condition Timing ..................................... 212
Transmission ................................................... 214
Multi-Master Communication, Bus Collision
and Arbitration ................................................. 218
Multi-Master Mode ................................................... 218
Operation ................................................................. 196
Read/Write Bit Information (R/W Bit) ............... 196, 197
Registers ................................................................. 192
Serial Clock (RC3/SCK/SCL) ................................... 197
Slave Mode .............................................................. 196
Addressing ....................................................... 196
Reception ........................................................ 197
Transmission ................................................... 197
Sleep Operation ....................................................... 218
Stop Condition Timing ............................................. 217
ID Locations ............................................................. 283, 297
INCF ................................................................................ 320
INCFSZ ............................................................................ 321
In-Circuit Debugger .......................................................... 297
In-Circuit Serial Programming (ICSP) ...................... 283, 297
Indexed Literal Offset Addressing
and Standard PIC18 Instructions ............................. 346
Indexed Literal Offset Mode ............................................. 346
Indirect Addressing ............................................................ 81
INFSNZ ............................................................................ 321
Initialization Conditions for all Registers ...................... 57–60
Instruction Cycle ................................................................ 67
Clocking Scheme ....................................................... 67
Instruction Flow/Pipelining ................................................. 67
Instruction Set .................................................................. 299
ADDLW .................................................................... 305
ADDWF .................................................................... 305
ADDWF (Indexed Literal Offset Mode) .................... 347
DS41303B-page 408
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