PIC18F23K20 Datasheet, PDF (379/420 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2XK20/4XK20
TABLE 26-9: CLKOUT AND I/O TIMING REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ
Max Units Conditions
10 TosH2ckL OSC1 ↑ to CLKOUT ↓
—
75
200
ns
11
TosH2ckH OSC1 ↑ to CLKOUT ↑
—
75
200
ns
12 TckR
CLKOUT Rise Time
—
35
100
ns
13 TckF
CLKOUT Fall Time
—
35
100
ns
14 TckL2ioV CLKOUT ↓ to Port Out Valid
—
— 0.5 TCY + 20 ns
15 TioV2ckH Port In Valid before CLKOUT ↑
0.25 TCY + 25 —
—
ns
16 TckH2ioI Port In Hold after CLKOUT ↑
0
—
—
ns
17 TosH2ioV OSC1 ↑ (Q1 cycle) to Port Out Valid
—
50
150
ns
18 TosH2ioI OSC1 ↑ (Q2 cycle) to Port Input Invalid
(I/O in hold time)
100
—
—
ns
19 TioV2osH Port Input Valid to OSC1 ↑ (I/O in setup time)
0
—
—
ns
20 TioR
Port Output Rise Time
—
10
25
ns
21 TioF
Port Output Fall Time
—
10
25
ns
22† TINP
INT pin High or Low Time
TCY
—
—
ns
23† TRBP
RB7:RB4 Change INT High or Low Time
TCY
—
—
ns
24† TRCP
RC7:RC4 Change INT High or Low Time
20
ns
† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKOUT output is 4 x TOSC.
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
FIGURE 26-6:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
I/O pins
Note: Refer to Figure 26-3 for load conditions.
30
31
34
34
© 2007 Microchip Technology Inc.
Advance Information
DS41303B-page 377