PIC18F2455_09 Datasheet, PDF (73/438 Pages) Microchip Technology – 28/40/44-Pin,High-Performance,Enhanced Flash,USB Microcontrollers with nanoWatt Technology

PIC18F2455/2550/4455/4550
TABLE 5-2: REGISTER FILE SUMMARY (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page
EEADR
EEDATA
EECON2
EECON1
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
TRISE⁽³⁾
TRISD⁽³⁾
TRISC
TRISB
TRISA
LATE⁽³⁾
LATD⁽³⁾
LATC
LATB
LATA
PORTE
PORTD⁽³⁾
PORTC
PORTB
PORTA
UEP15
UEP14
UEP13
UEP12
UEP11
UEP10
UEP9
UEP8
UEP7
UEP6
UEP5
UEP4
UEP3
UEP2
UEP1
UEP0
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
EEPROM Address Register
0000 0000 55, 91
EEPROM Data Register
0000 0000 55, 91
EEPROM Control Register 2 (not a physical register)
0000 0000 55, 82
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
xx-0 x000 55, 83
OSCFIP
CMIP
USBIP
EEIP
BCLIP
HLVDIP
TMR3IP
CCP2IP 1111 1111 56, 109
OSCFIF
CMIF
USBIF
EEIF
BCLIF
HLVDIF
TMR3IF
CCP2IF 0000 0000 56, 105
OSCFIE
SPPIP⁽³⁾
SPPIF⁽³⁾
SPPIE⁽³⁾
CMIE
ADIP
ADIF
ADIE
USBIE
RCIP
RCIF
RCIE
EEIE
TXIP
TXIF
TXIE
BCLIE
SSPIP
SSPIF
SSPIE
HLVDIE
CCP1IP
CCP1IF
CCP1IE
TMR3IE
TMR2IP
TMR2IF
TMR2IE
CCP2IE
TMR1IP
TMR1IF
TMR1IE
0000 0000
1111 1111
0000 0000
0000 0000
56, 107
56, 108
56, 104
56, 106
INTSRC
—
—
TUN4
TUN3
TUN2
TUN1
TUN0 0--0 0000 56, 28
—
—
—
—
—
TRISE2
TRISE1
TRISE0 ---- -111 56, 126
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0 1111 1111 56, 124
TRISC7
TRISC6
—
—
—
TRISC2
TRISC1
TRISC0 11-- -111 56, 121
TRISB7
—
TRISB6
TRISA6⁽⁴⁾
TRISB5
TRISA5
TRISB4
TRISA4
TRISB3
TRISA3
TRISB2
TRISA2
TRISB1
TRISA1
TRISB0
TRISA0
1111 1111 56, 118
-111 1111 56, 115
—
—
—
—
—
LATE2
LATE1
LATE0 ---- -xxx 56, 126
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0 xxxx xxxx 56, 124
LATC7
LATC6
—
—
—
LATC2
LATC1
LATC0 xx-- -xxx 56, 121
LATB7
—
RDPU⁽³⁾
LATB6
LATA6⁽⁴⁾
—
LATB5
LATA5
—
LATB4
LATA4
—
LATB3
LATA3
RE3⁽⁵⁾
LATB2
LATA2
RE2⁽³⁾
LATB1
LATA1
RE1⁽³⁾
LATB0
LATA0
RE0⁽³⁾
xxxx xxxx
-xxx xxxx
0--- x000
56, 118
56, 115
56, 125
RD7
RC7
RD6
RC6
RD5
RC5⁽⁶⁾
RD4
RC4⁽⁶⁾
RD3
—
RD2
RC2
RD1
RC1
RD0
RC0
xxxx xxxx 56, 124
xxxx -xxx 56, 121
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx 56, 118
—
RA6⁽⁴⁾
RA5
RA4
RA3
RA2
RA1
RA0
-x0x 0000 56, 115
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Bit 21 of the TBLPTRU allows access to the device Configuration bits.
The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
I²C™ Slave mode only.
© 2009 Microchip Technology Inc.
DS39632E-page 71