PIC18F2455_09 Datasheet, PDF (127/438 Pages) Microchip Technology – 28/40/44-Pin,High-Performance,Enhanced Flash,USB Microcontrollers with nanoWatt Technology

PIC18F2455/2550/4455/4550
10.5 PORTE, TRISE and LATE
Registers
Depending on the particular PIC18F2455/2550/4455/
4550 device selected, PORTE is implemented in two
different ways.
For 40/44-pin devices, PORTE is a 4-bit wide port.
Three pins (RE0/AN5/CK1SPP, RE1/AN6/CK2SPP
and RE2/AN7/OESPP) are individually configurable as
inputs or outputs. These pins have Schmitt Trigger
input buffers. When selected as an analog input, these
pins will read as ‘0’s.
The corresponding Data Direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISE bit
(= 0) will make the corresponding PORTE pin an output
(i.e., put the contents of the output latch on the selected
pin).
In addition to port data, the PORTE register
(Register 10-1) also contains the RDPU control bit
(PORTE<7>); this enables or disables the weak
pull-ups on PORTD.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
Note: On a Power-on Reset, RE2:RE0 are
configured as analog inputs.
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
REGISTER 10-1: PORTE REGISTER
R/W-0
U-0
RDPU⁽³⁾
—
bit 7
U-0
U-0
—
—
The fourth pin of PORTE (MCLR/VPP/RE3) is an input
only pin. Its operation is controlled by the MCLRE Config-
uration bit. When selected as a port pin (MCLRE = 0), it
functions as a digital input only pin; as such, it does not
have TRIS or LAT bits associated with its operation.
Otherwise, it functions as the device’s Master Clear input.
In either configuration, RE3 also functions as the
programming voltage input during programming.
Note:
On a Power-on Reset, RE3 is enabled as
a digital input only if Master Clear
functionality is disabled.
EXAMPLE 10-5: INITIALIZING PORTE
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVLW
MOVWF
MOVWF
PORTE
LATE
0Ah
ADCON1
03h
07h
CMCON
TRISC
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Configure A/D
; for digital inputs
; Value used to
; initialize data
; direction
; Turn off
; comparators
; Set RE<0> as inputs
; RE<1> as outputs
; RE<2> as inputs
10.5.1 PORTE IN 28-PIN DEVICES
For 28-pin devices, PORTE is only available when Mas-
ter Clear functionality is disabled (MCLRE = 0). In these
cases, PORTE is a single bit, input only port comprised
of RE3 only. The pin operates as previously described.
R/W-x
RE3^(1,2)
R/W-0
RE2⁽³⁾
R/W-0
RE1⁽³⁾
R/W-0
RE0⁽³⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6-4
bit 3-0
RDPU: PORTD Pull-up Enable bit
1 = PORTD pull-ups are enabled by individual port latch values
0 = All PORTD pull-ups are disabled
Unimplemented: Read as ‘0’
RE3:RE0: PORTE Data Input bits^(1,2,3)
Note 1:
2:
3:
implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0); otherwise,
read as ‘0’.
RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
Unimplemented in 28-pin devices; read as ‘0’.
© 2009 Microchip Technology Inc.
DS39632E-page 125