PIC18F2455_09 Datasheet, PDF (198/438 Pages) Microchip Technology – 28/40/44-Pin,High-Performance,Enhanced Flash,USB Microcontrollers with nanoWatt Technology

PIC18F2455/2550/4455/4550
TABLE 18-1: REGISTERS ASSOCIATED WITH THE STREAMING PARALLEL PORT
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
SPPCON⁽³⁾
—
—
—
—
—
— SPPOWN SPPEN
57
SPPCFG⁽³⁾ CLKCFG1 CLKCFG0 CSEN CLK1EN WS3
WS2
WS1
WS0
57
SPPEPS⁽³⁾ RDSPP WRSPP
— SPPBUSY ADDR3 ADDR2 ADDR1 ADDR0
57
SPPDATA⁽³⁾ DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
57
PIR1
SPPIF⁽³⁾ ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF
56
PIE1
SPPIE⁽³⁾ ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE
56
IPR1
SPPIP⁽³⁾ ADIP
RCIP
TXIP
SSPIP CCP1IP TMR2IP TMR1IP
56
PORTE
RDPU⁽³⁾
—
—
—
RE3^(1,2) RE2⁽³⁾
RE1⁽³⁾
RE0⁽³⁾
56
Legend:
Note 1:
2:
3:
— = unimplemented, read as ‘0’. Shaded cells are not used for the Streaming Parallel Port.
Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
These registers and/or bits are unimplemented on 28-pin devices.
DS39632E-page 196
© 2009 Microchip Technology Inc.