PIC18F2455_09 Datasheet, PDF (47/438 Pages) Microchip Technology – 28/40/44-Pin,High-Performance,Enhanced Flash,USB Microcontrollers with nanoWatt Technology

PIC18F2455/2550/4455/4550
4.0 RESET
The PIC18F2455/2550/4455/4550 devices differentiate
between various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during power-managed modes
d) Watchdog Timer (WDT) Reset (during
execution)
e) Programmable Brown-out Reset (BOR)
f) RESET Instruction
g) Stack Full Reset
h) Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 5.1.2.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 25.2 “Watchdog
Timer (WDT)”.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 4-1.
4.1 RCON Register
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the regis-
ter indicate that a specific Reset event has occurred. In
most cases, these bits can only be cleared by the event
and must be set by the application after the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in Section 4.6 “Reset State
of Registers”.
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 9.0 “Interrupts”. BOR is covered in
Section 4.4 “Brown-out Reset (BOR)”.
FIGURE 4-1:
RESET
Instruction
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Stack
Pointer
Stack Full/Underflow Reset
External Reset
MCLR
MCLRE
( )_IDLE
Sleep
WDT
Time-out
VDD Rise POR Pulse
Detect
VDD
Brown-out
Reset
BOREN
S
OSC1
OST/PWRT
OST
1024 Cycles
10-Bit Ripple Counter
Chip_Reset
R
Q
32 μs
INTRC⁽¹⁾
PWRT 65.5 ms
11-Bit Ripple Counter
Note 1: This is the low-frequency INTRC source from the internal oscillator block.
2: See Table 4-2 for time-out situations.
Enable PWRT
Enable OST⁽²⁾
© 2009 Microchip Technology Inc.
DS39632E-page 45