PIC18F2455_09 Datasheet, PDF (389/438 Pages) Microchip Technology – 28/40/44-Pin,High-Performance,Enhanced Flash,USB Microcontrollers with nanoWatt Technology

PIC18F2455/2550/4455/4550
28.4.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 28-5:
EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
CLKO
1
3
3
4
4
2
TABLE 28-8: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
1A
1
2
3
4
Note 1:
2:
FOSC
TOSC
External CLKI Frequency⁽¹⁾
Oscillator Frequency⁽¹⁾
External CLKI Period⁽¹⁾
Oscillator Period⁽¹⁾
DC
0.2
4
4
20.8
1000
48
1
25⁽²⁾
24⁽²⁾
DC
5000
MHz
MHz
MHz
MHz
ns
ns
EC, ECIO Oscillator mode
XT, XTPLL Oscillator mode
HS Oscillator mode
HSPLL Oscillator mode
EC, ECIO Oscillator mode
XT Oscillator mode
40
250
ns HS Oscillator mode
TCY
Instruction Cycle Time⁽¹⁾
40
83.3
250
ns HSPLL Oscillator mode
DC
ns TCY = 4/FOSC
TosL,
External Clock in (OSC1)
30
TosH
High or Low Time
10
—
ns XT Oscillator mode
—
ns HS Oscillator mode
TosR, External Clock in (OSC1)
—
TosF
Rise or Fall Time
—
20
ns XT Oscillator mode
7.5
ns HS Oscillator mode
Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
When VDD >= 3.3V, the maximum crystal or resonator frequency is 25 MHz (or 24 MHz with PLL prescaler).
When 2.0V < VDD < 3.3V, the maximum crystal frequency = (16.36 MHz/V)(VDD – 2.0V) + 4 MHz.
© 2009 Microchip Technology Inc.
DS39632E-page 387