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PIC18F2455_09 Datasheet, PDF (70/438 Pages) Microchip Technology – 28/40/44-Pin,High-Performance,Enhanced Flash,USB Microcontrollers with nanoWatt Technology
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PIC18F2455/2550/4455/4550
5.3.5 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM in the data memory space.
SFRs start at the top of data memory and extend down-
ward to occupy the top segment of Bank 15, from F60h
to FFFh. A list of these registers is given in Table 5-1
and Table 5-2.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this
section. Registers related to the operation of a
peripheral feature are described in the chapter for that
peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
TABLE 5-1: SPECIAL FUNCTION REGISTER MAP
Address
Name
Address
Name
Address
Name
FFFh
FFEh
FFDh
FFCh
FFBh
TOSU
TOSH
TOSL
STKPTR
PCLATU
FDFh INDF2(1)
FDEh POSTINC2(1)
FDDh POSTDEC2(1)
FDCh PREINC2(1)
FDBh PLUSW2(1)
FBFh
FBEh
FBDh
FBCh
FBBh
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
FFAh
FF9h
PCLATH
PCL
FDAh
FD9h
FSR2H
FSR2L
FBAh CCP2CON
FB9h
—(2)
FF8h TBLPTRU
FD8h STATUS
FB8h BAUDCON
FF7h TBLPTRH
FD7h TMR0H
FB7h ECCP1DEL
FF6h TBLPTRL
FD6h TMR0L
FB6h ECCP1AS
FF5h
FF4h
TABLAT
PRODH
FD5h
FD4h
T0CON
—(2)
FB5h CVRCON
FB4h CMCON
FF3h PRODL
FD3h OSCCON
FB3h TMR3H
FF2h INTCON
FD2h HLVDCON
FB2h TMR3L
FF1h INTCON2
FD1h WDTCON
FB1h T3CON
FF0h INTCON3
FEFh INDF0(1)
FEEh POSTINC0(1)
FEDh POSTDEC0(1)
FECh PREINC0(1)
FEBh PLUSW0(1)
FEAh FSR0H
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
FCAh
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
FB0h
FAFh
FAEh
FADh
FACh
FABh
FAAh
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
—(2)
FE9h FSR0L
FC9h SSPBUF
FA9h EEADR
FE8h WREG
FE7h INDF1(1)
FE6h POSTINC1(1)
FE5h POSTDEC1(1)
FE4h PREINC1(1)
FE3h PLUSW1(1)
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
EEDATA
EECON2(1)
EECON1
—(2)
—(2)
—(2)
FE2h FSR1H
FC2h ADCON0
FA2h
IPR2
FE1h FSR1L
FC1h ADCON1
FA1h
PIR2
FE0h
BSR
FC0h ADCON2
FA0h
PIE2
Address Name
F9Fh IPR1
F9Eh PIR1
F9Dh
F9Ch
PIE1
—(2)
F9Bh
F9Ah
F99h
F98h
F97h
F96h
F95h
OSCTUNE
—(2)
—(2)
—(2)
—(2)
TRISE(3)
TRISD(3)
F94h TRISC
F93h TRISB
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
TRISA
—(2)
—(2)
—(2)
—(2)
LATE(3)
LATD(3)
F8Bh LATC
F8Ah LATB
F89h
F88h
F87h
F86h
F85h
LATA
—(2)
—(2)
—(2)
—(2)
F84h PORTE
F83h PORTD(3)
F82h PORTC
F81h PORTB
F80h PORTA
Address Name
F7Fh UEP15
F7Eh UEP14
F7Dh UEP13
F7Ch UEP12
F7Bh UEP11
F7Ah UEP10
F79h UEP9
F78h UEP8
F77h UEP7
F76h UEP6
F75h UEP5
F74h UEP4
F73h UEP3
F72h UEP2
F71h UEP1
F70h UEP0
F6Fh UCFG
F6Eh UADDR
F6Dh UCON
F6Ch USTAT
F6Bh UEIE
F6Ah UEIR
F69h
UIE
F68h
UIR
F67h UFRMH
F66h
F65h
F64h
F63h
F62h
F61h
F60h
UFRML
SPPCON(3)
SPPEPS(3)
SPPCFG(3)
SPPDATA(3)
—(2)
—(2)
Note 1:
2:
3:
Not a physical register.
Unimplemented registers are read as ‘0’.
These registers are implemented only on 40/44-pin devices.
DS39632E-page 68
© 2009 Microchip Technology Inc.
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