PIC24FJ64GA004-IPT Datasheet, PDF (49/52 Pages) Microchip Technology – PIC24FJXXXGA0XX Flash Programming Specification

PIC24FJXXXGA0XX
7.0 AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS
Standard Operating Conditions
Operating Temperature: 0°C to +70°C. Programming at +25°C is recommended.
Param
No.
Symbol
Characteristic
Min
Max Units
Conditions
D111 VDD Supply Voltage During Programming
VDDCORE + 0.1 3.60
V Normal programming^(1,2)
D112 IPP
Programming Current on MCLR
—
5
μA
D113 IDDP Supply Current During Programming
—
2
mA
D031 VIL
Input Low Voltage
VSS
0.2 VDD V
D041 VIH
Input High Voltage
0.8 VDD
VDD
V
D080 VOL
Output Low Voltage
—
0.4
V IOL = 8.5 mA @ 3.6V
D090 VOH Output High Voltage
3.0
—
V IOH = -3.0 mA @ 3.6V
D012 CIO
Capacitive Loading on I/O pin (PGDx)
—
50
pF To meet AC specifications
D013 CF
Filter Capacitor Value on VCAP
4.7
10
μF Required for controller core
P1 TPGC Serial Clock (PGCx) Period
100
—
ns
P1A TPGCL Serial Clock (PGCx) Low Time
40
—
ns
P1B TPGCH Serial Clock (PGCx) High Time
40
—
ns
P2 TSET1 Input Data Setup Time to Serial Clock ↑
15
—
ns
P3 THLD1 Input Data Hold Time from PGCx ↑
15
—
ns
P4 TDLY1 Delay Between 4-Bit Command and
Command Operand
40
—
ns
P4A TDLY1A Delay Between 4-Bit Command Operand
40
and Next 4-Bit Command
—
ns
P5 TDLY2 Delay Between Last PGCx ↓ of Command
20
Byte to First PGCx ↑ of Read of Data Word
—
ns
P6 TSET2 VDD ↑ Setup Time to MCLR ↑
100
—
ns
P7 THLD2 Input Data Hold Time from MCLR ↑
25
—
ms
P8 TDLY3 Delay Between Last PGCx ↓ of Command
12
Byte to PGDx ↑ by Programming Executive
—
μs
P9 TDLY4 Programming Executive Command
Processing Time
40
—
μs
P10 TDLY6 PGCx Low Time After Programming
400
—
ns
P11 TDLY7 Chip Erase Time
400
—
ms
P12 TDLY8 Page Erase Time
40
—
ms
P13 TDLY9 Row Programming Time
2
—
ms
P14 TR
MCLR Rise Time to Enter ICSP™ mode
—
1.0
μs
P15 TVALID Data Out Valid from PGCx ↑
10
—
ns
P16 TDLY10 Delay Between Last PGCx ↓ and MCLR ↓
0
—
s
P17 THLD3 MCLR ↓ to VDD ↓
100
—
ns
P18 TKEY1 Delay from First MCLR ↓ to First PGCx ↑
40
for Key Sequence on PGDx
—
ns
P19 TKEY2 Delay from Last PGCx ↓ for Key
1
Sequence on PGDx to Second MCLR ↑
—
ms
P20 TDLY11 Delay Between PGDx ↓ by Programming
23
Executive to PGDx Driven by Host
—
µs
P21 TDLY12 Delay Between Programming Executive
8
Command Response Words
—
ns
Note 1:
2:
VDDCORE must be supplied to the VDDCORE/VCAP pin if the on-chip voltage regulator is disabled. See Section 2.1
“Power Requirements” for more information. (Minimum VDDCORE allowing Flash programming is 2.25V.)
VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be within ±0.3V
of VDD and VSS, respectively.
© 2008 Microchip Technology Inc.
DS39768D-page 49