PIC24FJ64GA004-IPT Datasheet, PDF (17/52 Pages) Microchip Technology – PIC24FJXXXGA0XX Flash Programming Specification

PIC24FJXXXGA0XX
TABLE 3-4: SERIAL INSTRUCTION EXECUTION FOR CHIP ERASE
Command
(Binary)
Data
(Hex)
Description
Step 1: Exit the Reset vector.
0000
0000
0000
000000
040200
000000
NOP
GOTO
NOP
0x200
Step 2: Set the NVMCON to erase all program memory.
0000
0000
2404FA
MOV
#0x404F, W10
883B0A
MOV
W10, NVMCON
Step 3: Set TBLPAG and perform dummy table write to select what portions of memory are erased.
0000
0000
0000
0000
0000
0000
200000
880190
200000
BB0800
000000
000000
MOV
MOV
MOV
TBLWTL
NOP
NOP
#<PAGEVAL>, W0
W0, TBLPAG
#0x0000, W0
W0,[W0]
Step 4: Initiate the erase cycle.
0000
0000
0000
A8E761
000000
000000
BSET
NOP
NOP
NVMCON, #WR
Step 5: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.
0000
0000
0000
0000
0000
0001
0000
040200
000000
803B02
883C22
000000
<VISI>
000000
GOTO 0x200
NOP
MOV
NVMCON, W2
MOV
W2, VISI
NOP
Clock out contents of the VISI register.
NOP
© 2008 Microchip Technology Inc.
DS39768D-page 17