PIC24FJ64GA004-IPT Datasheet, PDF (48/52 Pages) Microchip Technology – PIC24FJXXXGA0XX Flash Programming Specification

PIC24FJXXXGA0XX
TABLE 6-4: CHECKSUM COMPUTATION (CONTINUED)
Device
Read Code
Protection
Checksum Computation
Erased
Checksum
Value
Checksum with
0xAAAAAA at 0x0 and Last
Code Address
PIC24FJ128GAGA006
Disabled
Enabled
CFGB + SUM(0:0157FB)
0
0xF8CC
0x0000
PIC24FJ128GAGA008
Disabled
Enabled
CFGB + SUM(0:0157FB)
0
0xF8CC
0x0000
PIC24FJ128GAGA010
Disabled
Enabled
CFGB + SUM(0:0157FB)
0
0xF8CC
0x0000
Legend: Item
Description
SUM[a:b] = Byte sum of locations, a to b inclusive (all 3 bytes of code memory)
CFGB = Configuration Block (masked),
64/80/100-Pin Devices = Byte sum of (CW1 & 0x7DDF + CW2 & 0x87E3)
28/44-Pin Devices = Byte sum of (CW1 & 0x7FDF + CW2 & 0xFFF7)
Note: CW1 address is last location of implemented program memory; CW2 is (last location – 2).
0xF6CE
0x0000
0xF6CE
0x0000
0xF6CE
0x0000
DS39768D-page 48
© 2008 Microchip Technology Inc.