PIC24FJ64GA004-IPT Datasheet, PDF (10/52 Pages) Microchip Technology – PIC24FJXXXGA0XX Flash Programming Specification

PIC24FJXXXGA0XX
2.4 Memory Map
The program memory map extends from 000000h to
FFFFFEh. Code storage is located at the base of the
memory map and supports up to 44K instruction words
(about 128 Kbytes). Table 2-3 shows the program
memory size and number of erase and program blocks
present in each device variant. Each erase block, or
page, contains 512 instructions, and each program
block, or row, contains 64 instructions.
Locations 800000h through 8007FEh are reserved for
executive code memory. This region stores the
programming executive and the debugging executive.
The programming executive is used for device pro-
gramming and the debugging executive is used for
in-circuit debugging. This region of memory can not be
used to store user code.
The last two implemented program memory locations
are reserved for the device Configuration registers.
TABLE 2-2:
FLASH CONFIGURATION
WORD LOCATIONS FOR
PIC24FJXXXGA0XX DEVICES
Device
Configuration Word
Addresses
1
2
PIC24FJ16GA
PIC24FJ32GA
PIC24FJ48GA
PIC24FJ64GA
PIC24FJ96GA
PIC24FJ128GAGA
002BFEh
0057FEh
0083FEh
00ABFEh
00FFFEh
0157FEh
002BFCh
0057FCh
0083FCh
00ABFCh
00FFFCh
0157FCh
Locations, FF0000h and FF0002h, are reserved for the
Device ID registers. These bits can be used by the
programmer to identify what device type is being
programmed. They are described in Section 6.1
“Device ID”. The Device ID registers read out
normally, even after code protection is applied.
Figure 2-4 shows the memory map for the
PIC24FJXXXGA0XX family variants.
TABLE 2-3:
Device
PIC24FJ16GA
PIC24FJ32GA
PIC24FJ48GA
PIC24FJ64GA
PIC24FJ96GA
PIC24FJ128GA
CODE MEMORY SIZE
User Memory
Address Limit
(Instruction Words)
Write
Blocks
Erase
Blocks
002BFEh (5.5K)
88
11
0057FEh (11K)
176
22
0083FEh (16.5K)
264
33
00ABFEh (22K)
344
43
00FFFEh (32K)
512
64
0157FEh (44K)
688
86
DS39768D-page 10
© 2008 Microchip Technology Inc.