PIC24FJ64GA004-IPT Datasheet, PDF (25/52 Pages) Microchip Technology – PIC24FJXXXGA0XX Flash Programming Specification

3.10 Verify Code Memory and
Configuration Word
The verify step involves reading back the code memory
space and comparing it against the copy held in the
programmer’s buffer. The Configuration registers are
verified with the rest of the code.
The verify process is shown in the flowchart in
Figure 3-8. Memory reads occur a single byte at a time,
so two bytes must be read to compare against the word
in the programmer’s buffer. Refer to Section 3.8
“Reading Code Memory” for implementation details
of reading code memory.
Note:
Because the Configuration registers
include the device code protection bit,
code memory should be verified immedi-
ately after writing if code protection is
enabled. This is because the device will
not be readable or verifiable if a device
Reset occurs after the code-protect bit in
CW1 has been cleared.
FIGURE 3-8:
VERIFY CODE
MEMORY FLOW
Start
Set TBLPTR = 0
Read Low Byte
with Post-Increment
Read High Byte
with Post-Increment
Does
Word = Expect
Data?
Yes
No
Failure,
Report
Error
All
No
code memory
verified?
Yes
Done
PIC24FJXXXGA0XX
3.11 Reading the Application ID Word
The Application ID Word is stored at address 8005BEh
in executive code memory. To read this memory
location, you must use the SIX control code to move
this program memory location to the VISI register.
Then, the REGOUT control code must be used to clock
the contents of the VISI register out of the device. The
corresponding control and instruction codes that must
be serially transmitted to the device to perform this
operation are shown in Table 3-10.
After the programmer has clocked out the Application
ID Word, it must be inspected. If the Application ID has
the value, BBh, the programming executive is resident
in memory and the device can be programmed using
the mechanism described in Section 4.0 “Device
Programming – Enhanced ICSP”. However, if the
Application ID has any other value, the programming
executive is not resident in memory; it must be loaded
to memory before the device can be programmed. The
procedure for loading the programming executive to
memory is described in Section 5.4 “Programming
the Programming Executive to Memory”.
3.12 Exiting ICSP Mode
Exiting Program/Verify mode is done by removing VIH
from MCLR, as shown in Figure 3-9. The only require-
ment for exit is that an interval, P16, should elapse
between the last clock and program signals on PGCx
and PGDx before removing VIH.
FIGURE 3-9:
EXITING ICSP™ MODE
MCLR
P16 _P17
VIH
VDD
VIH
PGDx
PGCx
PGD = Input
© 2008 Microchip Technology Inc.
DS39768D-page 25