PIC24FJ64GA004-IPT Datasheet, PDF (3/52 Pages) Microchip Technology – PIC24FJXXXGA0XX Flash Programming Specification

PIC24FJXXXGA0XX
2.2 Program Memory Write/Erase
Requirements
The Flash program memory on the PIC24FJXXXGA0XX
devices has a specific write/erase requirement that must
be adhered to for proper device operation. The rule is
that any given word in memory must not be written more
than twice before erasing the page in which it is located.
Thus, the easiest way to conform to this rule is to write
all the data in a programming block within one write
cycle. The programming methods specified in this
specification comply with this requirement.
Note: Writing to a location multiple times without
erasing is not recommended.
2.3 Pin Diagrams
The pin diagrams for the PIC24FJXXXGA0XX family
are shown in the following figures. The pins that are
required for programming are listed in Table 2-1 and
are shown in bold letters in the figures. Refer to the
appropriate device data sheet for complete pin
descriptions.
TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING)
Pin Name
Pin Name
Pin Type
During Programming
Pin Description
MCLR
MCLR
P
Programming Enable
ENVREG
DISVREG⁽¹⁾
VDD and AVDD⁽²⁾
VSS and AVSS⁽²⁾
ENVREG
DISVREG
VDD
VSS
I
Enable for On-Chip Voltage Regulator
I
Disable for On-Chip Voltage Regulator
P
Power Supply
P
Ground
VDDCORE
VDDCORE
P
Regulated Power Supply for Core
PGC1
PGC
I
Primary Programming Pin Pair: Serial Clock
PGD1
PGD
I/O
Primary Programming Pin Pair: Serial Data
PGC2
PGC
I
Secondary Programming Pin Pair: Serial Clock
PGD2
PGD
I/O
Secondary Programming Pin Pair: Serial Data
Legend: I = Input, O = Output, P = Power
Note 1: Applies to 28 and 44-pin devices only.
2: All power supply and ground pins must be connected, including analog supplies (AVDD) and ground
(AVSS).
© 2008 Microchip Technology Inc.
DS39768D-page 3