PIC24FJ64GA004-IPT Datasheet, PDF (23/52 Pages) Microchip Technology – PIC24FJXXXGA0XX Flash Programming Specification

PIC24FJXXXGA0XX
3.8 Reading Code Memory
Reading from code memory is performed by executing
a series of TBLRD instructions and clocking out the data
using the REGOUT command.
Table 3-8 shows the ICSP programming details for
reading code memory. In Step 1, the Reset vector is
exited. In Step 2, the 24-bit starting source address for
reading is loaded into the TBLPAG register and W6
register. The upper byte of the starting source address
is stored in TBLPAG and the lower 16 bits of the source
address are stored in W6.
To minimize the reading time, the packed instruction
word format that was utilized for writing is also used for
reading (see Figure 3-6). In Step 3, the Write Pointer,
W7, is initialized. In Step 4, two instruction words are
read from code memory and clocked out of the device,
through the VISI register, using the REGOUT
command. Step 4 is repeated until the desired amount
of code memory is read.
TABLE 3-8: SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY
Command
(Binary)
Data
(Hex)
Description
Step 1: Exit Reset vector.
0000
0000
0000
000000
040200
000000
NOP
GOTO
NOP
0x200
Step 2: Initialize TBLPAG and the Read Pointer (W6) for TBLRD instruction.
0000
0000
0000
200xx0
MOV
880190
MOV
2xxxx6
MOV
#<SourceAddress23:16>, W0
W0, TBLPAG
#<SourceAddress15:0>, W6
Step 3: Initialize the Write Pointer (W7) to point to the VISI register.
0000
0000
207847
MOV
000000
NOP
#VISI, W7
Step 4: Read and clock out the contents of the next two locations of code memory, through the VISI register, using
the REGOUT command.
0000
0000
0000
0001
0000
0000
0000
0000
0000
0000
0000
0001
0000
0000
0000
0000
0001
0000
BA0B96
000000
000000
<VISI>
000000
BADBB6
000000
000000
BAD3D6
000000
000000
<VISI>
000000
BA0BB6
000000
000000
<VISI>
000000
TBLRDL [W6], [W7]
NOP
NOP
Clock out contents of VISI register
NOP
TBLRDH.B [W6++], [W7++]
NOP
NOP
TBLRDH.B [++W6], [W7--]
NOP
NOP
Clock out contents of VISI register
NOP
TBLRDL [W6++], [W7]
NOP
NOP
Clock out contents of VISI register
NOP
Step 5: Reset device internal PC.
0000
0000
040200
000000
GOTO
NOP
0x200
Step 6: Repeat Steps 4 and 5 until all desired code memory is read.
© 2008 Microchip Technology Inc.
DS39768D-page 23