PIC24FJ64GA004-IPT Datasheet, PDF (15/52 Pages) Microchip Technology – PIC24FJXXXGA0XX Flash Programming Specification

PIC24FJXXXGA0XX
3.3 Entering ICSP Mode
As shown in Figure 3-4, entering ICSP Program/Verify
mode requires three steps:
1. MCLR is briefly driven high, then low.
2. A 32-bit key sequence is clocked into PGDx.
3. MCLR is then driven high within a specified
period of time and held.
The programming voltage applied to MCLR is VIH,
which is essentially VDD in the case of
PIC24FJXXXGA0XX devices. There is no minimum
time requirement for holding at VIH. After VIH is
removed, an interval of at least P18 must elapse before
presenting the key sequence on PGDx.
The key sequence is a specific 32-bit pattern:
‘0100 1101 0100 0011 0100 1000 0101 0001’
(more easily remembered as 4D434851h in hexa-
decimal). The device will enter Program/Verify mode only
if the sequence is valid. The Most Significant bit (MSb) of
the most significant nibble must be shifted in first.
Once the key sequence is complete, VIH must be
applied to MCLR and held at that level for as long as
Program/Verify mode is to be maintained. An interval of
at least time, P19 and P7, must elapse before present-
ing data on PGDx. Signals appearing on PGCx before
P7 has elapsed will not be interpreted as valid.
On successful entry, the program memory can be
accessed and programmed in serial fashion. While in
ICSP mode, all unused I/Os are placed in the
high-impedance state.
FIGURE 3-4:
P6
MCLR
ENTERING ICSP™ MODE
P14
VIH
P19 P7
VIH
VDD
PGDx
PGCx
Program/Verify Entry Code = 4D434851h
0 1 0 0 1 ... 0 0 0 1
b31 b30 b29 b28 b27
b3 b2 b1 b0
P18
P1A
P1B
© 2008 Microchip Technology Inc.
DS39768D-page 15